F0_DB_MREP_MRD_LAT_27 (DDRMC_DDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_DB_MREP_MRD_LAT_27 (DDRMC_DDR4_XRAM) Register Description

Register NameF0_DB_MREP_MRD_LAT_27
Offset Address0x00000049A4
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionData Buffer Read Latency

LRDIMM Data Buffer Read Calibration Stage: MRD latency and MREP phase. Permuted by nibbles and ranks.

F0_DB_MREP_MRD_LAT_27 (DDRMC_DDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
mrd_latency 8:6roRead-only0x0MRD Latency
mrep_phase 5:0roRead-only0x0MREP Phase