F0_DM_DBI_EN (DDRMC_DDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_DM_DBI_EN (DDRMC_DDR4_XRAM) Register Description

Register NameF0_DM_DBI_EN
Offset Address0x0000000288
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionData Mask and DBI setting

F0_DM_DBI_EN (DDRMC_DDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 2:0roRead-only0x0DDR4 Settings
000: Both DM and DBI are disabled
001: DM is enabled
010: Write DBI is enabled
100: Read DBI is enabled
110: Read and Write DBI are enabled