F0_LP4_MR13 (DDRMC_LPDDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_LP4_MR13 (DDRMC_LPDDR4_XRAM) Register Description

Register NameF0_LP4_MR13
Offset Address0x0000000270
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionLP4 MR13 Contents

F0_LP4_MR13 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 8:0roRead-only0x0MR13 values for LPDDR4