F0_MR2_17_9 (DDRMC_LPDDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_MR2_17_9 (DDRMC_LPDDR4_XRAM) Register Description

Register NameF0_MR2_17_9
Offset Address0x0000000230
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionMR2 Contents, MSB

F0_MR2_17_9 (DDRMC_LPDDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 8:0roRead-only0x0MR2 values, the upper 9 bits