F0_WRDQDBI_STG2_DQS_ODLY_11 (DDRMC_DDR4_XRAM) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

F0_WRDQDBI_STG2_DQS_ODLY_11 (DDRMC_DDR4_XRAM) Register Description

Register NameF0_WRDQDBI_STG2_DQS_ODLY_11
Offset Address0x000000347C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionWRDQDBI Stage 2 DQS Odelay

Write DQ/DBI Deskew Calibration stage: Odelay for DQS after reverting. Permuted by byte lanes.

F0_WRDQDBI_STG2_DQS_ODLY_11 (DDRMC_DDR4_XRAM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Value 8:0roRead-only0x0WRDQDBI Stage 2 DQS Odelay