MGCHK_CTRL (DDRMC_DDR4_XRAM) Register Description
| Register Name | MGCHK_CTRL |
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| Offset Address | 0x0000001F80 |
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| Absolute Address |
This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Margin Check Control |
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Margin Check Control Register
MGCHK_CTRL (DDRMC_DDR4_XRAM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| mgchk_enable_status | 6 | roRead-only | 0x0 | Margin Check Enable Status |
| mgchk_error | 5 | roRead-only | 0x0 | Margin Check Error |
| mgchk_done | 4 | roRead-only | 0x0 | Margin Check Done |
| mgchk_ack | 3 | roRead-only | 0x0 | Margin Check Acknowledge |
| mgchk_enable | 2 | rwNormal read/write | 0x0 | Margin Check Enable |
| mgchk_abort | 1 | rwNormal read/write | 0x0 | Margin Check Abort |
| mgchk_start | 0 | rwNormal read/write | 0x0 | Margin Check Request |