REG_IER0 (CMT_XPLL) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_IER0 (CMT_XPLL) Register Description

Register NameREG_IER0
Offset Address0x000000001C
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

REG_IER0 (CMT_XPLL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0Reseved for future use
LOCK_B 0woWrite-only0x0Description