REG_PCSR_STATUS (CMT_XPLL) Register

NoC and Integrated Memory Controller NPI Register Reference (AM019)

Document ID
AM019
Release Date
2023-11-17
Revision
1.1

REG_PCSR_STATUS (CMT_XPLL) Register Description

Register NameREG_PCSR_STATUS
Offset Address0x0000000008
Absolute Address This register description shows register offset addresses relative to the base address of the module. Base addresses vary from one device to another. To determine the correct base address for any device, refer to support.xilinx.com/s/article/00003507.
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000001
DescriptionProgramming Status Register

REG_PCSR_STATUS (CMT_XPLL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:14razRead as zero0x0Reserved for future use.
HARD_FAIL_OR13:11roRead-only0x0The HARD_FAIL bits are used for test of the PCSR triple-redundant flip-flops.
HARD_FAIL_AND10:8roRead-only0x0The HARD_FAIL bits are used for test of the PCSR triple-redundant flip-flops.
MEM_CLEAR_PASS 7roRead-only0x0This bit is asserted by the DFx controller if MBIST completed successfully.
MEM_CLEAR_DONE 6roRead-only0x0This bit is asserted by the DFx controller when MBIST has completed.
CALERROR 5roRead-only0x0This bit should be asserted by the COE if any error occurs during calibration.
CALDONE 4roRead-only0x0This bit will be set to 1 by the COE to indicate that the block has completed its calibration.
INCAL 3roRead-only0x0When asserted this bit indicates that the block is currently running a calibration or locking operation.
This bit is set by the COE.
SCAN_CLEAR_PASS 2roRead-only0x0When set to 1 this bit indicates the scan-clear operation has completed successfully.
This bit is set by the COE scan-clear logic.
SCAN_CLEAR_DONE 1roRead-only0x0When asserted this bit indicates that the scan-clear operation has been completed.
This bit is set by the COE scan-clear logic.
PCSRLOCK 0roRead-only0x1When asserted this bit indicates that the NPI slave address space is locked.
This includes the PCR.