AIE-ML Architecture

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID: AM020
Release Date: 2022-09-28
Revision: 1.0 English

Overview
Introduction to Versal ACAP
Navigating Content by Design Process
Motivation to AIE-ML
AIE-ML Array Features
AIE-ML Array Overview
AIE-ML Array Hierarchy
Performance
Memory Error Handling
AIE-ML Tile Architecture
Memory Mapped AXI4 Interconnect
AXI4-Stream Interconnect
AIE-ML Tile Program Memory
AIE-ML Interfaces
AIE-ML Memory Module
AIE-ML Data Movement Architecture
AIE-ML to AIE-ML Data Communication via Local Memory
AIE-ML Tile to AIE-ML Tile Data Communication via Memory and DMA
AIE-ML Tile to AIE-ML Tile Data Communication via AXI4-Stream Interconnect
AIE-ML to PL Data Communication via Shared Memory
AIE-ML Data Movement with Memory Tiles
AIE-ML Debug
AIE-ML Trace and Profiling
Trace
Profiling (Performance Counters)
AIE-ML Events
AIE-ML Array Interface Architecture
AIE-ML Array Interface
Features of the AIE-ML Array Interface
Array Interface Memory-Mapped AXI4 Slave Interconnect
Array Interface DMA Memory-Mapped AXI4 Master Interface
Array Interface AXI4-Stream Interconnect
AIE-ML to Programmable Logic Interface
AIE-ML to NoC Interface AXI-Stream
Interrupt Handling
AIE-ML Architecture
Functional Overview
Register Files
Instruction Fetch and Decode Unit
Load and Store Unit
Scalar Unit
Arithmetic Logic Unit and Scalar Functions
Vector Unit
Fixed-Point Vector Unit
Floating-Point Vector Unit
Register Move Functionality
AIE-ML Memory Tile Architecture
AIE-ML Memory Tile Overview and Features
AIE-ML Memory Tile Memory
AIE-ML Memory Tile DMA
AIE-ML Memory Tile Locks Module and Stream Switch
AIE-ML Configuration and Boot
AIE-ML Array Configuration
AIE-ML Boot Sequence
AIE-ML Array Reconfiguration
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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