AIE-ML Array Hierarchy

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English
The AIE-ML array is made up of AIE-ML tiles, one or two rows of AIE-ML memory tiles, and AIE-ML array interface tiles (the last row of the array). The types of interface tiles include the AIE-ML to PL and AIE-ML to NoC interface tiles. There is also exactly one configuration interface tile in each AIE-ML array that contains a PLL for AIE-ML clock generation and other global control functions. The following figure shows a conceptual view of the complete tile hierarchy associated with the AIE-ML array. See AIE-ML Tile Architecture and AIE-ML Array Interface Architecture for detailed descriptions of the various tiles.
Figure 1. Hierarchy of Tiles in an AIE-ML Array