AIE-ML Array Interface

The AIE-ML array interface consists of PL and NoC interface tiles. There is also one configuration interface tile per device. The following figure shows the array interface connectivity that the AIE-ML array uses to communicate with other blocks in the Versal architecture. Also specified are the number of streams in the AXI4-Stream interconnect interfacing with the PL, NoC, or AIE-ML tiles, and between the AXI4-Stream switches.

Tip: The exact number of PL and NoC interface tiles is device specific. The Versal Architecture and Product Data Sheet: Overview (DS950) lists the size of the AIE-ML array.

Figure 1. AIE-ML Array Interface Topology

Note: The AIE-ML F_MAX is 1 GHz for the -1L speed grade devices. The PL clock should be set at half that speed to 500 MHz. There is also a clock domain crossing at the NoC interface tile between the clocks for the AIE-ML and the NoC.

The types of interfaces to the PL and NoC are:

Memory-mapped AXI4 interface: the communication channel is from the NSU to the AIE-ML as a slave
AXI4-Stream interconnect has four types of interfaces:
- Connection to stream switches in other tiles
- Bi-directional connection to the PL streaming interface
- Connection to the array interface DMA that generates traffic into the NoC using a memory-mapped AXI4 interface
- Direct connection to the NoC streaming interfaces (NSU and NMU)

The AIE-ML array interface tiles manage the two high performance interfaces:

AIE-ML to PL
AIE-ML to NoC

The following tables summarize the bandwidth performance of the AIE-ML array interface with the PL, the NoC, and the AIE-ML tile. The bandwidth performances are specified per each AIE-ML column for the -1L speed grade devices. There is a reduction in the number of connections per column between the PL to AIE-ML interface and the AXI4-Stream switch to the AIE-ML tile. This is to support the horizontally connected stream switches that provide additional horizontal routing capability. The total bandwidth for the various devices across speed grades can be found in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) or Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958).

Table 1. AIE-ML Array Interface to PL Interface Bandwidth Performance
Connection Type	Number of Connections	Data Width (bits)	Clock Domain	Bandwidth per Connection (GB/s)	Aggregate Bandwidth (GB/s)
PL to AIE-ML array interface	8	64¹	PL (500 MHz)	4	32
AIE-ML array interface to PL	6	64	PL (500 MHz)	4	24
AIE-ML array interface to AXI4-Stream switch	8	32	AIE-ML (1 GHz)	4	32
AXI4-Stream switch to AIE-ML array interface	6	32	AIE-ML (1 GHz)	4	24
Horizontal interface between AXI4-Stream switches²	4	32	AIE-ML (1 GHz)	4	16
All streams to and from the PL are 64 bits on the PL side. The streams can be converted to 32-bit wide, but only one 32-bit word is valid out of the 64-bit wide stream. Two 64-bit wide streams can be combined to form a 128-bit wide stream, but the number of connections are halved. The aggregate bandwidth shown is in the east/west direction. There are two sets of connections going in and out of each AXI4-Stream switch.

Table 2. AIE-ML Array Interface to NoC AXI4-Stream Interface Bandwidth Performance
Connection Type	Number of Connections	Data Width (bits)	Clock Domain	Bandwidth per Connection (GB/s)	Aggregate Bandwidth (GB/s)
AIE-ML to NoC (NoC side)	1	128	NoC Interface (960 MHz)¹	16	16
AIE-ML to NoC (AIE-ML side)	4	32	AIE-ML (1 GHz)	4	16
NoC to AIE-ML (NoC side)	1	128	NoC Interface (960 MHz)¹	16	16
NoC to AIE-ML (AIE-ML side)	4	32	AIE-ML (1 GHz)	4	16
The frequency is based off of a –1 speed grade.

Table 3. AIE-ML Array Interface to AIE-ML Tile Bandwidth Performance
Connection Type	Number of Connections	Data Width (bits)	Clock Domain	Bandwidth per Connection (GB/s)	Aggregate Bandwidth (GB/s)
AXI4-Stream switch to AIE-ML tile	6	32	AIE-ML (1 GHz)	4	24
AIE-ML tile to AXI4-Stream switch	4	32	AIE-ML (1 GHz)	4	16

The following sections contain additional AIE-ML array interface descriptions. The AIE-ML tiles are described in the AIE-ML Tile Architecture chapter.