The AIE-ML array interface consists of PL and NoC interface tiles. There is also one configuration interface tile per device. The following figure shows the array interface connectivity that the AIE-ML array uses to communicate with other blocks in the Versal architecture. Also specified are the number of streams in the AXI4-Stream interconnect interfacing with the PL, NoC, or AIE-ML tiles, and between the AXI4-Stream switches.
The types of interfaces to the PL and NoC are:
- Memory-mapped AXI4 interface: the communication channel is from the NSU to the AIE-ML as a slave
-
AXI4-Stream interconnect has four types of
interfaces:
- Connection to stream switches in other tiles
- Bi-directional connection to the PL streaming interface
- Connection to the array interface DMA that generates traffic into the NoC using a memory-mapped AXI4 interface
- Direct connection to the NoC streaming interfaces (NSU and NMU)
The AIE-ML array interface tiles manage the two high performance interfaces:
- AIE-ML to PL
- AIE-ML to NoC
The following tables summarize the bandwidth performance of the AIE-ML array interface with the PL, the NoC, and the AIE-ML tile. The bandwidth performances are specified per each AIE-ML column for the -1L speed grade devices. There is a reduction in the number of connections per column between the PL to AIE-ML interface and the AXI4-Stream switch to the AIE-ML tile. This is to support the horizontally connected stream switches that provide additional horizontal routing capability. The total bandwidth for the various devices across speed grades can be found in the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) or Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958).
Connection Type | Number of Connections | Data Width (bits) | Clock Domain | Bandwidth per Connection (GB/s) | Aggregate Bandwidth (GB/s) |
---|---|---|---|---|---|
PL to AIE-ML array interface | 8 | 64 1 | PL (500 MHz) |
4 | 32 |
AIE-ML array interface to PL | 6 | 64 | PL (500 MHz) |
4 | 24 |
AIE-ML array interface to AXI4-Stream switch | 8 | 32 |
AIE-ML
(1 GHz) |
4 | 32 |
AXI4-Stream switch to AIE-ML array interface | 6 | 32 |
AIE-ML
(1 GHz) |
4 | 24 |
Horizontal interface between AXI4-Stream switches 2 | 4 | 32 |
AIE-ML
(1 GHz) |
4 | 16 |
|
Connection Type | Number of Connections | Data Width (bits) | Clock Domain | Bandwidth per Connection (GB/s) | Aggregate Bandwidth (GB/s) |
---|---|---|---|---|---|
AIE-ML to NoC (NoC side) | 1 | 128 | NoC Interface (960 MHz) 1 |
16 | 16 |
AIE-ML to NoC (AIE-ML side) | 4 | 32 |
AIE-ML
(1 GHz) |
4 | 16 |
NoC to AIE-ML (NoC side) | 1 | 128 | NoC Interface (960 MHz) 1 |
16 | 16 |
NoC to AIE-ML (AIE-ML side) | 4 | 32 |
AIE-ML
(1 GHz) |
4 | 16 |
|
Connection Type | Number of Connections | Data Width (bits) | Clock Domain | Bandwidth per Connection (GB/s) | Aggregate Bandwidth (GB/s) |
---|---|---|---|---|---|
AXI4-Stream switch to AIE-ML tile | 6 | 32 |
AIE-ML
(1 GHz) |
4 | 24 |
AIE-ML tile to AXI4-Stream switch | 4 | 32 |
AIE-ML
(1 GHz) |
4 | 16 |
The following sections contain additional AIE-ML array interface descriptions. The AIE-ML tiles are described in the AIE-ML Tile Architecture chapter.