AIE-ML Array Interface Architecture

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English

The AIE-ML is arranged in a 2D array as shown in the following figure. The AIE-ML array interface provides the necessary functionality to interface with the rest of the device. The AIE-ML array interface has three types of AIE-ML interface tiles. There is a one-to-one correspondence of interface tiles for every column of the AIE-ML array. The interface tiles form a row and move memory-mapped AXI4 and AXI4-Stream data horizontally (left and right) and also vertically up a AIE-ML tile column. The AIE-ML interface tiles are based on a modular architecture, but the final composition is device specific. Refer to the following figure for the internal hierarchy of the AIE-ML array interface in the AIE-ML array.

Figure 1. AIE-ML Array Interface Hierarchy

The types of array interface tiles and the modules within them are described in this section.

  • AIE-ML PL interface tile
    • PL module includes:
      • AXI4-Stream switch
      • Memory-mapped AXI4 switch
      • AIE-ML to PL stream interface
      • Control, debug, and trace unit
  • AIE-ML configuration interface tile (exactly one instance per AIE-ML array)
    • PLL for AIE-ML clock generation
    • Power-on-reset (POR) unit
    • Interrupt generation unit
    • Dynamic function exchange (DFx) logic
    • NoC peripheral interconnect (NPI) unit
    • AIE-ML array global registers that control global features such as PLL/clock control, secure/non-secure behavior, interrupt controllers, global reset control, and DFx logic
  • AIE-ML NoC interface tile
    • PL module (see previous description)
    • NoC module with interfaces to NMU and NSU includes:
      • Bi-directional NoC streaming interface
      • Array interface DMA