AIE-ML Data Movement with Memory Tiles

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English

The AIE-ML Memory tile is introduced in the AIE-ML architecture to significantly increase the on-chip memory inside the AIE-ML array. This new functional unit reduced the utilization of PL resources including block RAMs and URAMs in ML applications. The following figure illustrates the general concept:

Figure 1. AIE-ML Data Movement and Use of Memory Tile

Depending on the characteristics of the ML applications and bandwidth requirement, the AIE-ML data movement architecture supports different dataflow mappings where either the activations and/or the weights are stored in the AIE-ML memory tiles. The following figure shows examples of data alternative mappings supported by the AIE-ML architecture.

Figure 2. Dataflow Mappings

Figure 3. Data From External Memory to AIE-ML Array
Figure 4. Data Copy from AIE-ML Array to External Memory