AIE-ML Debug

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English

Debugging the AIE-ML uses the memory-mapped AXI4 interface. All the major components in the AIE-ML array are memory mapped.

  • Program memories
  • Data memories
  • AIE-ML registers
  • DMA registers
  • Lock module registers
  • Stream switch registers
  • AIE-ML break points registers
  • Events and performance counters registers

These memory-mapped registers can be read and/or written from any master that can produce memory-mapped AXI4 interface requests (PS, PL, and PMC). These requests come through the NoC to the AIE-ML array interface, and then to the target tile in the array. The following figure shows a typical debugging setup involving a software development environment running on a host development system combined with its integrated debugger.

Figure 1. Overview of the AIE-ML Debug Interface

The debugger connects to the platform management controller (PMC) on an AIE-ML enabled Versal device either using a JTAG connection or the Xilinx high-speed debug port (HSDP) connection.