Memory tiles are added in AIE-ML, not in AIE. See AIE-ML Tile Architecture for more information. The following figure shows the AIE-ML memory tile architecture.
Figure 1. AIE-ML Memory Tile Architecture
The following is a high-level list of AIE-ML memory tile features:
- 512 KB memory arranged in 16 banks, ECC protected
- Supports up to 30 GB/s read and 30 GB/s write in parallel per memory tile
- DMA channels can directly access memory in the nearest neighbor memory tiles to the east and west
- Memory to stream DMA (MM2S) with six channels and support for 4D tensor address generation, zero-padding insertion, and compression. Accesses memory and locks in east and west neighboring tiles. Supports task queue and task-complete-tokens.
- Stream to memory DMA (S2MM) with six channels and support for 4D tensor address generation, out-of-order packet transfer, finish-on-TLAST, and decompression. Accesses memory and locks in east and west neighboring tiles. Supports task queue and task-complete-tokens.
- Stream switch in the AIE-ML memory tile shares the same design as the AIE-ML tile. There are 17 master ports and 18 slave ports, but no east or west streams.
- Locks module is accessible from neighboring AIE-ML memory tile DMA channels; there are 64 semaphore locks and each lock state is 6-bit unsigned.
- Additional control and status registers
- Configuration/debug interconnect with a 1 MB memory-mapped AXI4 address space per tile
- Debug and trace similar to that in the AIE-ML tile.