AIE-ML Memory Tile Memory

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English

Each AIE-ML memory tile has 512 KB of memory as 16 banks of 32 KB. Each bank is 128 bits wide and 2k words deep. Each bank allows one read or one write every cycle and can be accessed by nine read interfaces and nine write interfaces. Each interface is 128-bit. The following block diagrams show the memory tile read and write interfaces.

Figure 1. Memory Tile Memory Read Interfaces

Figure 2. Memory Tile Memory Write Interfaces

The interfaces also have the following features:

Read Interfaces
Memory-mapped AXI4 write including control packets for memory tile –1 and memory tile +1, and six MM2S channels [0-5]
Write Interfaces
Memory-mapped AXI4 read including control packets for memory tile –1 and memory tile +1, and six S2MM channels [0-5]

The memory in the memory tile supports configurable bank interleaving. The banks can be addressed in linear or interleaved mode. The setting is controlled by the register bit Memory_Interleaving (0 = No memory interleaving; 1 = 16 banks interleaving).

In linear mode, addressing starts at bank 0, address 0, 1, 2, and so on until the last address, then the address is address 0, 1, 2, of bank 1 and so on. In interleaved mode, address starts at bank 0, address 0 and then bank1, address 0 until bank (N-1) address 0, and the next address is bank 0, address 1, and so on.

The memory tile banks have ECC protection and the ECC scrubbing is similar to the AIE-ML data memory.