AIE-ML Tile to AIE-ML Tile Data Communication via Memory and DMA

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English

The communication described in the previous section is inside an AIE-ML tile or between two neighboring AIE-ML tiles. For non-neighboring AIE-ML tiles, a similar communication can be established using the DMA in the memory module associated with each AIE-ML tile, as shown in the following figure. The synchronization of the ping-pong buffers in each memory module is carried out by the locks in a similar manner to the AIE-ML to AIE-ML Data Communication via Local Memory section. In comparison to the neighboring tile communication, the main differences in this mode are increased communication latency and memory resources.

Figure 1. Data Communication Between Two Non-neighboring AIE-ML Tiles