AIE-ML to Programmable Logic Interface

Versal ACAP AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2022-09-28
Revision
1.0 English

AXI4-Stream switches in the AIE-ML to PL tiles can directly communicate with the programmable logic using the AXI4-Stream interface. There are six streams from AIE-ML to PL and eight streams from PL to each AIE-ML column. From a bandwidth perspective, each AXI4-Stream interface can support the following.

  • 24 GB/s from each AIE-ML column to PL
  • 32 GB/s from PL to each AIE-ML column

All bandwidth calculations assume a nominal 1 GHz AIE-ML clock for the -1L speed grade devices at VCCINT = 0.70V.