Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
- System and Solution Planning
Identifying the components, performance, I/O, and
data transfer requirements at a system level.
Includes application mapping for the solution to PS,
PL, and AI Engine. Topics in this document that apply to this design process
- Overview provides an overview of the AIE-ML architecture and includes:
- AIE-ML Tile Architecture describes the interaction between the memory module and the interconnect and between the AIE-ML and the memory module.
- AIE-ML Array Interface Architecture is a high-level view of the AIE-ML array interface to the PL and NoC.
- AIE-ML Architecture describes the processor functional unit and register files.
- AIE-ML Memory Tile Architecture describes the features and functionality of the AIE-ML memory tile, which is an additional functional unit in the AIE-ML architecture.
- AIE-ML Configuration and Boot describes configuring the AIE-ML array from the processing system during boot and reconfiguration.
- AI Engine Development
- Creating the AI Engine graph and kernels, library use, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels. Topics in this document that apply to this design process include: