The AIE-ML array has a single clock domain for all the tiles and array interface blocks. The performance target of the AIE-ML array for the -1L speed grade devices is 1 GHz with VCCINT at 0.70V. In addition, the AIE-ML array has clocks for interfacing to other blocks. The following table summarizes the various clocks in the AIE-ML array and their performance targets. For more information, see Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) or Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958).
|Target for -1L
|Relation to AIE-ML Clock
|AIE-ML array clock
|Asynchronous, clock domain crossing (CDC) within the NoC
|Asynchronous, CDC within AIE-ML array interface