Versal ACAP AIE-ML Architecture Manual (AM020)

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1.0 English
The AIE-ML array has a single clock domain for all the tiles and array interface blocks. The performance target of the AIE-ML array for the -1L speed grade devices is 1 GHz with VCCINT at 0.70V. In addition, the AIE-ML array has clocks for interfacing to other blocks. The following table summarizes the various clocks in the AIE-ML array and their performance targets. For more information, see Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) or Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958).
Table 1. AIE-ML Interfacing Clock Domains
Clock Target for -1L Source Relation to AIE-ML Clock
AIE-ML array clock 1 GHz AIE-ML PLL N/A
NoC clock 960 MHz NoC clocking Asynchronous, clock domain crossing (CDC) within the NoC
PL clocks 500 MHz PL clocking Asynchronous, CDC within AIE-ML array interface
NPI clock 300 MHz NPI clocking Asynchronous