Summary

Versal ACAP AIE-ML Architecture Manual (AM020)
Document ID
AM020
Release Date
2023-02-15
Revision
1.1 English
Table 1. Summary of the Key Differences between AIE and AIE-ML
  AIE AIE-ML 1
Array structure Checkerboard All lines identical
Cascade interface 384-bits wide

Horizontal direction

 512-bits wide

Horizontal and vertical directions
Tile stream interface 2 × 32-bit in and 2 × out 32-bit out 1 × 32-bit in and 1 × out 32-bit out
Memory load/store per cycle 512/256 bits 512/256 bits
Advanced DSP functionality Yes No
INT4 operations/tile 256 1024 2
INT8 operations/tile 256 512
INT16 operations/tile 64 128
INT32 operations/tile 16 32 4
Bfloat16 float operations/tile – 256
FP32 float operations/tile 16 42 3
Data memory/tile 32 KB 64 KB
Program memory/tile 16 KB 16 KB
Memory tiles – 512 KB
Programmable logic (PL) to AIE array bandwidth 1X 1X
  1. In cases without sparsity and for ML applications
  2. Actually INT8 x INT4
  3. Emulation mode: The specified value gives 16b accuracy for the mantissa. The number is reduced for higher accuracy on the mantissa
  4. int32 × int32 can be emulated