Power and Electrical

The FPGA power can be estimated using Xilinx® Power Estimator or the Power Design Manager (PDM) tool. Estimates are shown in the following table. These calculations are made assuming dual PCIe Gen4 x8 mode.

Table 1. Power Estimates
Conditions¹	Zynq UltraScale+ RFSoC ZU48DR Power (W)³	Notes
Maximum PVT	38.1	Max Process, 100°C T_j ²
Typical PVT	33.1	Max Process, 75°C T_j ²
In all cases, the data flow through the FPGA is maxed out. T_j is FPGA die temperature. These are preliminary estimates and are not yet lab measured.