CLB Distributed RAM Switching Characteristics (SLICEM Only)

Sequential Delays

T_SHCKO

Clock to A – B outputs.

1.09

1.32

1.32

ns, Max

T_{SHCKO_1}

Clock to AMUX – BMUX outputs.

1.53

1.86

1.86

ns, Max

Setup and Hold Times Before/After Clock CLK

T_{DS_LRAM}/T_{DH_LRAM}

A – D inputs to CLK.

0.60/0.30

0.72/0.35

0.72/0.35

ns, Min

T_{AS_LRAM}/T_{AH_LRAM}

Address An inputs to clock.

0.30/0.60

0.37/0.70

0.37/0.70

ns, Min

Address An inputs through MUXs and/or carry logic to clock.

0.77/0.21

0.94/0.26

0.94/0.26

ns, Min

T_{WS_LRAM}/T_{WH_LRAM}

WE input to clock.

0.43/0.12

0.53/0.17

0.53/0.17

ns, Min

T_{CECK_LRAM}/T_{CKCE_LRAM}

CE input to CLK.

0.44/0.11

0.53/0.17

0.53/0.17

ns, Min

Clock CLK

T_{MPW_LRAM}

Minimum pulse width.

1.13

1.25

1.25

ns, Min

T_MCP

Minimum clock period.

2.26

2.50

2.50

ns, Min

Notes:

1.T_SHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.