CLB Shift Register Switching Characteristics (SLICEM Only)

Sequential Delays

T_REG

Clock to A – D outputs.

1.33

1.61

1.61

ns, Max

T_{REG_MUX}

Clock to AMUX – DMUX output.

1.77

2.15

2.15

ns, Max

T_{REG_M31}

Clock to DMUX output via M31 output.

1.23

1.46

1.46

ns, Max

Setup and Hold Times Before/After Clock CLK

T_{WS_SHFREG}/ T_{WH_SHFREG}

WE input.

0.41/0.12

0.51/0.17

0.51/0.17

ns, Min

T_{CECK_SHFREG}/ T_{CKCE_SHFREG}

CE input to CLK.

0.42/0.11

0.52/0.17

0.52/0.17

ns, Min

T_{DS_SHFREG}/ T_{DH_SHFREG}

A – D inputs to CLK.

0.37/0.37

0.44/0.43

0.44/0.43

ns, Min

Clock CLK

T_{MPW_SHFREG}

Minimum pulse width.

0.86

0.98

0.98

ns, Min