CLB Switching Characteristics

Combinatorial Delays

T_ILO

An – Dn LUT address to A.

0.11

0.13

0.13

ns, Max

T_{ILO_2}

An – Dn LUT address to AMUX/CMUX.

0.30

0.36

0.36

ns, Max

T_{ILO_3}

An – Dn LUT address to BMUX_A.

0.46

0.55

0.55

ns, Max

T_ITO

An – Dn inputs to A – D Q outputs.

1.05

1.27

1.27

ns, Max

T_AXA

AX inputs to AMUX output.

0.69

0.84

0.84

ns, Max

T_AXB

AX inputs to BMUX output.

0.66

0.83

0.83

ns, Max

T_AXC

AX inputs to CMUX output.

0.68

0.82

0.82

ns, Max

T_AXD

AX inputs to DMUX output.

0.75

0.90

0.90

ns, Max

T_BXB

BX inputs to BMUX output.

0.57

0.69

0.69

ns, Max

T_BXD

BX inputs to DMUX output.

0.69

0.82

0.82

ns, Max

T_CXC

CX inputs to CMUX output.

0.48

0.58

0.58

ns, Max

T_CXD

CX inputs to DMUX output.

0.59

0.71

0.71

ns, Max

T_DXD

DX inputs to DMUX output.

0.58

0.70

0.70

ns, Max

Sequential Delays

T_CKO

Clock to AQ – DQ outputs.

0.44

0.53

0.53

ns, Max

T_SHCKO

Clock to AMUX – DMUX outputs.

0.53

0.66

0.66

ns, Max

Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK

T_AS/T_AH

AN – DN input to CLK on A – D flip-flops.

0.09/0.14

0.11/0.18

0.11/0.18

ns, Min

T_DICK/T_CKDI

AX – DX input to CLK on A – D flip-flops.

0.07/0.21

0.09/0.26

0.09/0.26

ns, Min

AX – DX input through MUXs and/or carry logic to CLK on A – D flip-flops.

0.66/0.09

0.81/0.11

0.81/0.11

ns, Min

T_{CECK_CLB}/ T_{CKCE_CLB}

CE input to CLK on A – D flip-flops.

0.17/0.00

0.21/0.01

0.21/0.01

ns, Min

T_SRCK/T_CKSR

SR input to CLK on A – D flip-flops.

0.43/0.04

0.53/0.05

0.53/0.05

ns, Min

Set/Reset

T_SRMIN

SR input minimum pulse width.

0.78

1.04

1.04

ns, Min

T_RQ

Delay from SR input to AQ – DQ flip-flops.

0.59

0.71

0.71

ns, Max

T_CEO

Delay from CE input to AQ – DQ flip-flops.

0.58

0.70

0.70

ns, Max

F_TOG

Toggle frequency (for export control).

1286

1098

1098

MHz