Input Serializer/Deserializer Switching Characteristics

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  23:   ISERDES Switching Characteristics

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Setup/Hold for Control Lines

TISCCK_BITSLIP/ TISCKC_BITSLIP

BITSLIP pin setup/hold with respect to CLKDIV.

0.02/0.15

0.02/0.17

0.02/0.17

ns

TISCCK_CE/ TISCKC_CE

CE pin setup/hold with respect to CLK
(for CE1).

0.50/–0.01

0.72/–0.01

0.72/–0.01

ns

TISCCK_CE2/ TISCKC_CE2

CE pin setup/hold with respect to CLKDIV
(for CE2).

–0.10/0.36

–0.10/0.40

–0.10/0.40

ns

Setup/Hold for Data Lines

TISDCK_D/ TISCKD_D

D pin setup/hold with respect to CLK.

–0.02/0.14

–0.02/0.17

–0.02/0.17

ns

TISDCK_DDLY/ TISCKD_DDLY

DDLY pin setup/hold with respect to CLK (using IDELAY).(1)

–0.02/0.14

–0.02/0.17

–0.02/0.17

ns

TISDCK_D_DDR/ TISCKD_D_DDR

D pin setup/hold with respect to CLK at
DDR mode.

–0.02/0.14

–0.02/0.17

–0.02/0.17

ns

TISDCK_DDLY_DDR/ TISCKD_DDLY_DDR

D pin setup/hold with respect to CLK at
DDR mode (using IDELAY).(1)

0.14/0.14

0.17/0.17

0.17/0.17

ns

Sequential Delays

TISCKO_Q

CLKDIV to out at Q pin.

0.54

0.66

0.66

ns

Propagation Delays

TISDO_DO

D input to DO output pin.

0.11

0.13

0.13

ns

Notes:

1.Recorded at 0 tap value.