Symbol |
Description |
VCCINT Operating Voltage and Speed Grade |
Units |
||
---|---|---|---|---|---|
1.0V |
0.95V |
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-2 |
-1 |
-1L |
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Setup/Hold for Control Lines |
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TISCCK_BITSLIP/ TISCKC_BITSLIP |
BITSLIP pin setup/hold with respect to CLKDIV. |
0.02/0.15 |
0.02/0.17 |
0.02/0.17 |
ns |
TISCCK_CE/ TISCKC_CE |
CE pin setup/hold with respect to CLK |
0.50/–0.01 |
0.72/–0.01 |
0.72/–0.01 |
ns |
TISCCK_CE2/ TISCKC_CE2 |
CE pin setup/hold with respect to CLKDIV |
–0.10/0.36 |
–0.10/0.40 |
–0.10/0.40 |
ns |
Setup/Hold for Data Lines |
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TISDCK_D/ TISCKD_D |
D pin setup/hold with respect to CLK. |
–0.02/0.14 |
–0.02/0.17 |
–0.02/0.17 |
ns |
TISDCK_DDLY/ TISCKD_DDLY |
DDLY pin setup/hold with respect to CLK (using IDELAY).(1) |
–0.02/0.14 |
–0.02/0.17 |
–0.02/0.17 |
ns |
TISDCK_D_DDR/ TISCKD_D_DDR |
D pin setup/hold with respect to CLK at |
–0.02/0.14 |
–0.02/0.17 |
–0.02/0.17 |
ns |
TISDCK_DDLY_DDR/ TISCKD_DDLY_DDR |
D pin setup/hold with respect to CLK at |
0.14/0.14 |
0.17/0.17 |
0.17/0.17 |
ns |
Sequential Delays |
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TISCKO_Q |
CLKDIV to out at Q pin. |
0.54 |
0.66 |
0.66 |
ns |
Propagation Delays |
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TISDO_DO |
D input to DO output pin. |
0.11 |
0.13 |
0.13 |
ns |
Notes: |