Power-On/Off Power Supply Sequencing

The recommended power-on sequence is V_CCINT, V_CCBRAM, V_CCAUX, and V_CCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If V_CCINT and V_CCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If V_CCAUX and V_CCO have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously.

For V_CCO voltages of 3.3V in HR I/O banks and configuration bank 0 the following conditions apply.

·The voltage difference between V_CCO and V_CCAUX must not exceed 2.625V for longer than T_VCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.

·The T_VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.

There is no recommended sequence for supplies not discussed in this section.

Table: Power-On Current shows the minimum current, in addition to I_CCQ maximum, that is required by Spartan-7 devices for proper power-on and configuration. If the current minimums shown in Table: Power-On Current are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V_CCINT is applied. Once initialized and configured, use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate current drain on these supplies.