Revision History

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English

The following table shows the revision history for this document:

Date

Version

Description of Revisions

10/31/2022

1.10

In Table: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator(1), split -1Q speed grade into its own column.

03/13/2019

1.9

Removed FTGB196 package from XA7S6, XA7S15, XA7S25, and XA7S50 devices in Table: Package Skew(1).

09/28/2018

1.8

Removed description of -1Q speed grade only being available in XA Spartan-7 FPGAs from second paragraph of Introduction.

07/31/2018

1.7

In Table: Speed Specification Version By Device, updated Vivado tools version to 2018.2.1. In Table: Spartan-7 Device Speed Grade Designations, moved all speed grades for all devices to Production. In Table: Spartan-7 Device Production Software and Speed Specification Release, added Vivado tools version for XC7S6, XC7S15, XC7S75, XC7S100, XA7S6, XA7S15, XA7S75, and XA7S100.

06/18/2018

1.6

In Table: Speed Specification Version By Device, updated Vivado tools version to 2018.2. In Table: Spartan-7 Device Speed Grade Designations, moved all speed grades except -1Q (1.0V) for XC7S6 and XC7S15 to Production. In Table: Spartan-7 Device Production Software and Speed Specification Release, added Vivado tools version for XC7S6 and XC7S15.

04/04/2018

1.5

Added XA7S6, XA7S15, XA7S25, XA7S75, and XA7S100 devices throughout. In Table: Typical Quiescent Supply Current(1)(2)(3), updated typical quiescent supply current values for XC7S25 and XC7S50 devices, and added values for XC7S6, XC7S15, XC7S75, and XC7S100 devices. In Table: Power-On Current, updated table title and ICCINTMIN and ICCAUXMIN for XC7S75 and XC7S100 devices. In Table: Spartan-7 Device Speed Grade Designations, moved all speed grades for XC7S6 and XC7S15 to Preliminary, moved -1LI (0.95V) speed grade for XC7S25 to Production, and moved all speed grades except -1Q (1.0V) for XC7S75 and XC7S100 from Preliminary to Production. In Table: Spartan-7 Device Production Software and Speed Specification Release, added Vivado tools version for XC7S25, XC7S75, and XC7S100. In Table: Duty Cycle Distortion and Clock-Tree Skew, Table: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1), Table: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1), Table: Clock-Capable Clock Input to Output Delay With MMCM(1), Table: Clock-Capable Clock Input to Output Delay With PLL(1), Table: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks, Table: Clock-Capable Clock Input Setup and Hold With MMCM, and Table: Clock-Capable Clock Input Setup and Hold With PLL, changed parameter value for XA7S50 to N/A. In Table: Package Skew(1), added package skew values for XC7S6 and XC7S15 devices.

12/22/2017

1.4

In Table: Speed Specification Version By Device, updated Vivado tools version to 2017.4. In Table: Spartan-7 Device Speed Grade Designations, moved all speed grades for XC7S75 and XC7S100 from Advance to Preliminary and all speed grades except -1LI (0.95V) for XC7S25 from Advance to Production. In Table: Spartan-7 Device Production Software and Speed Specification Release, added Vivado tools version for XC7S25. Added Note 2 to Table: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator(1). In Table: Package Skew(1), added package skew values for XC7S25 device in CSGA324 package and XC7S75 and XC7S100 devices in FGGA676 package.

11/20/2017

1.3

Added XA7S50 device throughout. Updated description of offered temperature ranges in second paragraph of Introduction. Added row for junction temperature (Tj) at expanded (Q) temperature to Table: Recommended Operating Conditions(1)(2). Added -1Q (1.0V) speed grade to Table: Typical Quiescent Supply Current(1)(2)(3), and Table: Spartan-7 Device Speed Grade Designations to Table: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator(1). In Table: Speed Specification Version By Device, updated Vivado tools version to 2017.3. In Table: Package Skew(1), added package skew values for XC7S25, XC7S50, XC7S75, and XC7S100 devices in CSGA225, FTGB196, and FGGA484 packages. Added XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) to References.

06/20/2017

1.2

Updated paragraph before Table: Power-On Current. In Table: Speed Specification Version By Device, updated Vivado tools version to 2017.2. In Table: Spartan-7 Device Speed Grade Designations, moved all speed grades for XC7S50 from Preliminary to Production and updated Note 1. In Table: Spartan-7 Device Production Software and Speed Specification Release, added Vivado tools version for XC7S50. In Table: Package Skew(1), added package skew value for XC7S50 device in FGGA484 package.

04/07/2017

1.1

Added 1.35V to Note 5 in Table: Recommended Operating Conditions(1)(2). In Table: Speed Specification Version By Device, updated Vivado tools version to 2016.4. In Table: Spartan-7 Device Speed Grade Designations, moved all speed grades for XC7S50 from Advance to Preliminary. Removed SFI-4.1 and SPI-4.2 from descriptions of SDR LVDS receiver and DDR LVDS receiver, respectively, in Table: Networking Applications Interface Performances. In Table: Input/Output Delay Switching Characteristics, changed TIDELAYRESOLUTION units from ps to ┬Ás. Removed BUFMR from Note 1 in Table: Regional Clock Buffer Switching Characteristics (BUFR). In Table: Package Skew(1), replaced TQGA144 with FTGB196 for XC7S6, XC7S15, and XC7S25 devices, added FTGB196 package for XC7S50 device, and added package skew value for XC7S50 device in CSGA324 package.

09/27/2016

1.0

Initial Xilinx release.