Block RAM and FIFO Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2023-12-26
Revision
1.26 English
Table 1. Block RAM and FIFO Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Maximum Frequency
FMAX_WF_NC Block RAM (WRITE_FIRST and NO_CHANGE modes) 825 738 645 585 516 MHz
FMAX_RF Block RAM (READ_FIRST mode) 718 637 575 510 460 MHz
FMAX_FIFO FIFO in all modes without ECC 825 738 645 585 516 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration without PIPELINE 718 637 575 510 460 MHz
Block RAM and FIFO in ECC configuration with PIPELINE and Block RAM in WRITE_FIRST or NO_CHANGE mode 825 738 645 585 516 MHz
TPW 1 Minimum pulse width 495 542 543 577 578 ps
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO Clock CLK to DOUT output (without output register) 0.91 1.02 1.11 1.46 1.53 ns, Max
TRCKO_DO_REG Clock CLK to DOUT output (with output register) 0.27 0.29 0.30 0.42 0.44 ns, Max
  1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.