Device Pin-to-Pin Input Parameter Guidelines

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2023-12-26
Revision
1.26 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSFD_ZU1 Global clock input and input flip-flop (or latch) without MMCM Setup XCZU1 N/A 2.90 3.04 4.41 4.74 ns
TPHFD_ZU1 Hold –0.79 –0.79 –1.60 –1.60 ns
TPSFD_ZU2 Setup XCZU2 N/A 2.27 2.37 3.54 3.82 ns
TPHFD_ZU2 Hold –0.36 –0.36 –1.03 –1.03 ns
TPSFD_ZU3 Setup XCZU3 N/A 2.27 2.37 3.54 3.82 ns
TPHFD_ZU3 Hold –0.36 –0.36 –1.03 –1.03 ns
TPSFD_ZU3T Setup XCZU3T N/A 1.70 1.76 2.85 3.08 ns
TPHFD_ZU3T Hold –0.22 –0.22 –0.85 –0.85 ns
TPSFD_ZU4 Setup XCZU4 2.00 2.30 2.39 3.56 3.81 ns
TPHFD_ZU4 Hold –0.37 –0.37 –0.37 –1.05 –1.05 ns
TPSFD_ZU5 Setup XCZU5 2.00 2.30 2.39 3.56 3.81 ns
TPHFD_ZU5 Hold –0.37 –0.37 –0.37 –1.05 –1.05 ns
TPSFD_ZU6 Setup XCZU6 1.51 1.79 1.86 2.85 3.06 ns
TPHFD_ZU6 Hold –0.05 –0.05 –0.05 –0.60 –0.60 ns
TPSFD_ZU7 Setup XCZU7 2.02 2.32 2.42 3.59 3.87 ns
TPHFD_ZU7 Hold –0.40 –0.40 –0.40 –1.10 –1.10 ns
TPSFD_ZU9 Setup XCZU9 1.51 1.79 1.86 2.85 3.06 ns
TPHFD_ZU9 Hold –0.05 –0.05 –0.05 –0.60 –0.60 ns
TPSFD_ZU11 Setup XCZU11 1.99 2.28 2.38 3.54 3.79 ns
TPHFD_ZU11 Hold –0.38 –0.38 –0.38 –1.05 –1.05 ns
TPSFD_ZU15 Setup XCZU15 1.51 1.79 1.85 2.84 3.05 ns
TPHFD_ZU15 Hold –0.04 –0.04 –0.04 –0.60 –0.60 ns
TPSFD_ZU17 Setup XCZU17 2.00 2.29 2.38 3.56 3.83 ns
TPHFD_ZU17 Hold –0.38 –0.38 –0.38 –1.08 –1.08 ns
TPSFD_ZU19 Setup XCZU19 2.00 2.29 2.38 3.56 3.83 ns
TPHFD_ZU19 Hold –0.38 –0.38 –0.38 –1.08 –1.08 ns
TPSFD_XAZU1 Setup XAZU1 N/A N/A 3.04 N/A 4.74 ns
TPHFD_XAZU1 Hold N/A N/A -0.79 N/A -1.60 ns
TPSFD_XAZU2 Setup XAZU2 N/A N/A 2.37 N/A 3.82 ns
TPHFD_XAZU2 Hold N/A N/A –0.36 N/A –1.03 ns
TPSFD_XAZU3 Setup XAZU3 N/A N/A 2.37 N/A 3.82 ns
TPHFD_XAZU3 Hold N/A N/A –0.36 N/A –1.03 ns
TPSFD_XAZU3T Setup XAZU3T N/A N/A 1.76 N/A 3.08 ns
TPHFD_XAZU3T Hold N/A N/A –0.22 N/A –0.85 ns
TPSFD_XAZU4 Setup XAZU4 N/A N/A 2.39 N/A 3.81 ns
TPHFD_XAZU4 Hold N/A N/A –0.37 N/A –1.05 ns
TPSFD_XAZU5 Global clock input and input flip-flop (or latch) without MMCM Setup XAZU5 N/A N/A 2.39 N/A 3.81 ns
TPHFD_XAZU5 Hold N/A N/A –0.37 N/A –1.05 ns
TPSFD_XAZU7 Setup XAZU7 N/A N/A 2.42 N/A N/A ns
TPHFD_XAZU7 Hold N/A N/A –0.40 N/A N/A ns
TPSFD_XAZU11 Setup XAZU11 N/A N/A 2.38 N/A N/A ns
TPHFD_XAZU11 Hold N/A N/A –0.38 N/A N/A ns
TPSFD_XQZU3 Setup XQZU3 N/A 2.27 2.37 N/A 3.82 ns
TPHFD_XQZU3 Hold N/A –0.36 –0.36 N/A –1.03 ns
TPSFD_XQZU5 Setup XQZU5 N/A 2.30 2.39 N/A 3.81 ns
TPHFD_XQZU5 Hold N/A –0.37 –0.37 N/A –1.05 ns
TPSFD_XQZU7 Setup XQZU7 N/A 2.32 2.42 N/A 3.87 ns
TPHFD_XQZU7 Hold N/A –0.40 –0.40 N/A –1.10 ns
TPSFD_XQZU9 Setup XQZU9 N/A 1.79 1.86 N/A 3.06 ns
TPHFD_XQZU9 Hold N/A –0.05 –0.05 N/A –0.60 ns
TPSFD_XQZU11 Setup XQZU11 N/A 2.28 2.38 N/A 3.79 ns
TPHFD_XQZU11 Hold N/A –0.38 –0.38 N/A –1.05 ns
TPSFD_XQZU15 Setup XQZU15 N/A 1.79 1.85 N/A 3.05 ns
TPHFD_XQZU15 Hold N/A –0.04 –0.04 N/A –0.60 ns
TPSFD_XQZU19 Setup XQZU19 N/A 2.29 2.38 N/A 3.83 ns
TPHFD_XQZU19 Hold N/A –0.38 –0.38 N/A –1.08 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 2. Global Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSMMCMCC_ZU1 Global clock input and input flip-flop (or latch) with MMCM Setup XCZU1 N/A 1.34 1.40 1.34 1.40 ns
TPHMMCMCC_ZU1 Hold –0.17 –0.17 –0.17 –0.17 ns
TPSMMCMCC_ZU2 Setup XCZU2 N/A 1.83 1.96 1.83 1.96 ns
TPHMMCMCC_ZU2 Hold –0.19 –0.19 –0.24 –0.24 ns
TPSMMCMCC_ZU3 Setup XCZU3 N/A 1.83 1.96 1.83 1.96 ns
TPHMMCMCC_ZU3 Hold –0.19 –0.19 –0.24 –0.24 ns
TPSMMCMCC_ZU3T Setup XCZU3T N/A 1.96 2.10 1.96 2.10 ns
TPHMMCMCC_ZU3T Hold –0.14 –0.14 –0.16 –0.16 ns
TPSMMCMCC_ZU4 Setup XCZU4 1.82 1.82 1.94 1.82 1.94 ns
TPHMMCMCC_ZU4 Hold –0.16 –0.16 –0.16 –0.25 –0.25 ns
TPSMMCMCC_ZU5 Setup XCZU5 1.82 1.82 1.94 1.82 1.94 ns
TPHMMCMCC_ZU5 Hold –0.16 –0.16 –0.16 –0.25 –0.25 ns
TPSMMCMCC_ZU6 Setup XCZU6 2.00 2.00 2.12 2.00 2.12 ns
TPHMMCMCC_ZU6 Hold –0.11 –0.11 –0.11 –0.18 –0.18 ns
TPSMMCMCC_ZU7 Setup XCZU7 1.89 1.91 2.02 1.91 2.02 ns
TPHMMCMCC_ZU7 Hold –0.14 –0.14 –0.14 –0.18 –0.18 ns
TPSMMCMCC_ZU9 Setup XCZU9 2.00 2.00 2.12 2.00 2.12 ns
TPHMMCMCC_ZU9 Hold –0.11 –0.11 –0.11 –0.18 –0.18 ns
TPSMMCMCC_ZU11 Setup XCZU11 1.89 1.89 2.02 1.89 2.02 ns
TPHMMCMCC_ZU11 Hold –0.20 –0.20 –0.20 –0.25 –0.25 ns
TPSMMCMCC_ZU15 Setup XCZU15 1.99 1.99 2.12 1.99 2.12 ns
TPHMMCMCC_ZU15 Hold –0.10 –0.10 –0.10 –0.16 –0.16 ns
TPSMMCMCC_ZU17 Setup XCZU17 1.89 1.89 2.03 1.89 2.03 ns
TPHMMCMCC_ZU17 Hold –0.16 –0.16 –0.16 –0.23 –0.23 ns
TPSMMCMCC_ZU19 Setup XCZU19 1.89 1.89 2.03 1.89 2.03 ns
TPHMMCMCC_ZU19 Hold –0.16 –0.16 –0.16 –0.23 –0.23 ns
TPSMMCMCC_XAZU1 Setup XAZU1 N/A N/A 1.40 N/A 1.40 ns
TPHMMCMCC_XAZU1 Hold N/A N/A -0.17 N/A -0.17 ns
TPSMMCMCC_XAZU2 Setup XAZU2 N/A N/A 1.96 N/A 1.96 ns
TPHMMCMCC_XAZU2 Hold N/A N/A –0.19 N/A –0.24 ns
TPSMMCMCC_XAZU3 Setup XAZU3 N/A N/A 1.96 N/A 1.96 ns
TPHMMCMCC_XAZU3 Hold N/A N/A –0.19 N/A –0.24 ns
TPSMMCMCC_XAZU3T Setup XAZU3T N/A N/A 2.10 N/A 2.10 ns
TPHMMCMCC_XAZU3T Hold N/A N/A –0.14 N/A –0.16 ns
TPSMMCMCC_XAZU4 Setup XAZU4 N/A N/A 1.94 N/A 1.94 ns
TPHMMCMCC_XAZU4 Hold N/A N/A –0.16 N/A –0.25 ns
TPSMMCMCC_XAZU5 Setup XAZU5 N/A N/A 1.94 N/A 1.94 ns
TPHMMCMCC_XAZU5 Hold N/A N/A –0.16 N/A –0.25 ns
TPSMMCMCC_XAZU7 Global clock input and input flip-flop (or latch) with MMCM Setup XAZU7 N/A N/A 2.02 N/A N/A ns
TPHMMCMCC_XAZU7 Hold N/A N/A –0.14 N/A N/A ns
TPSMMCMCC_XAZU11 Setup XAZU11 N/A N/A 2.02 N/A N/A ns
TPHMMCMCC_XAZU11 Hold N/A N/A –0.20 N/A N/A ns
TPSMMCMCC_XQZU3 Setup XQZU3 N/A 1.83 1.96 N/A 1.96 ns
TPHMMCMCC_XQZU3 Hold N/A –0.19 –0.19 N/A –0.24 ns
TPSMMCMCC_XQZU5 Setup XQZU5 N/A 1.82 1.94 N/A 1.94 ns
TPHMMCMCC_XQZU5 Hold N/A –0.16 –0.16 N/A –0.25 ns
TPSMMCMCC_XQZU7 Setup XQZU7 N/A 1.91 2.02 N/A 2.02 ns
TPHMMCMCC_XQZU7 Hold N/A –0.14 –0.14 N/A –0.18 ns
TPSMMCMCC_XQZU9 Setup XQZU9 N/A 2.00 2.12 N/A 2.12 ns
TPHMMCMCC_XQZU9 Hold N/A –0.11 –0.11 N/A –0.18 ns
TPSMMCMCC_XQZU11 Setup XQZU11 N/A 1.89 2.02 N/A 2.02 ns
TPHMMCMCC_XQZU11 Hold –0.20 –0.20 –0.20 N/A –0.25 ns
TPSMMCMCC_XQZU15 Setup XQZU15 N/A 1.99 2.12 N/A 2.12 ns
TPHMMCMCC_XQZU15 Hold N/A –0.10 –0.10 N/A –0.16 ns
TPSMMCMCC_XQZU19 Setup XQZU19 N/A 1.89 2.03 N/A 2.03 ns
TPHMMCMCC_XQZU19 Hold N/A –0.16 –0.16 N/A –0.23 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 3. Sampling Window
Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
TSAMP_BUFG 1 510 610 610 610 610 ps
TSAMP_NATIVE_DPA 2 100 100 125 125 150 ps
TSAMP_NATIVE_BISC 3 60 60 85 85 110 ps
  1. This parameter indicates the total sampling error of the Zynq UltraScale+ MPSoC DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
  2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.
  3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).
Table 4. Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)
Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
TINPUT_LOGIC_UNCERTAINTY 1 40 ps
TCAL_ERROR 2 24 ps
  1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or ISERDESE3).
  2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance.