Integrated Interface Block for Interlaken

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document ID
DS925
Release Date
2023-12-26
Revision
1.26 English

More information and documentation on solutions using the integrated interface block for Interlaken can be found at UltraScale+ Interlaken . The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Zynq UltraScale+ MPSoC. This section describes the following Interlaken configurations.

  • 12 x 12.5 Gb/s protocol and lane logic mode (Table 1) .
  • 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s protocol and lane logic mode (Table 2) .
  • 12 x 25.78125 Gb/s lane logic only mode (Table 3) .
Table 1. Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode Designs
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
FRX_SERDES_CLK Receive serializer/ deserializer clock 195.32 195.32 195.32 195.32 195.32 MHz
FTX_SERDES_CLK Transmit serializer/ deserializer clock 195.32 195.32 195.32 195.32 195.32 MHz
FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 250.00 MHz
  Min 1 Max Min 1 Max Min 1 Max Min 1 Max Min 1 Max  
FCORE_CLK Interlaken core clock 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 MHz
FLBUS_CLK Interlaken local bus clock 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 300.00 322.27 MHz
  1. These are the minimum clock frequencies at the maximum lane performance.
Table 2. Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and Lane Logic Mode Designs
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 1 -2 1 -1 -2 -1
FRX_SERDES_CLK Receive serializer/ deserializer clock 440.79 440.79 N/A 402.84 N/A MHz
FTX_SERDES_CLK Transmit serializer/ deserializer clock 440.79 440.79 N/A 402.84 N/A MHz
FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 N/A 250.00 N/A MHz
  Min 2 Max Min 2 Max Min Max Min 2 Max Min Max  
FCORE_CLK Interlaken core clock 412.50 3 479.20 412.50 3 479.20 N/A 412.50 429.69 N/A MHz
FLBUS_CLK Interlaken local bus clock 300.00 4 349.52 300.00 4 349.52 N/A 300.00 349.52 N/A MHz
  1. 6 x 28.21 mode is only supported in the -2 (VCCINT = 0.85V) and -3 (VCCINT = 0.90V) speed grades.
  2. These are the minimum clock frequencies at the maximum lane performance.
  3. The minimum value for CORE_CLK is 451.36 MHz for the 6 x 28.21 Gb/s protocol.
  4. The minimum value for LBUS_CLK is 330.00 MHz for the 6 x 28.21 Gb/s protocol.
Table 3. Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
FRX_SERDES_CLK Receive serializer/ deserializer clock 402.84 402.84 N/A N/A N/A MHz
FTX_SERDES_CLK Transmit serializer/ deserializer clock 402.84 402.84 N/A N/A N/A MHz
FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 N/A N/A N/A MHz
FCORE_CLK Interlaken core clock 412.50 412.50 N/A N/A N/A MHz
FLBUS_CLK Interlaken local bus clock 349.52 349.52 N/A N/A N/A MHz