PS SPI Controller Interface

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)

Document ID: DS925
Release Date: 2023-12-26
Revision: 1.26 English

Table 1. SPI Interfaces
Symbol	Description¹	Min	Max	Units
SPI Master Interface
T_DCMSPICLK	SPI master mode clock duty cycle	45	55	%
T_MSPISSSCLK	Slave select asserted to first active clock edge	1²	–	F_{SPI_REF_CLK} cycles
T_MSPISCLKSS	Last active clock edge to slave select deasserted	1²	–	F_{SPI_REF_CLK} cycles
T_MSPIDCK	Input setup time for MISO	–2.0	–	ns
T_MSPICKD	Input hold time for MISO	0.3	–	F_MSPICLK cycles
T_MSPICKO	MOSI and slave select clock to out delay	–2.0	5.0	ns
F_MSPICLK	SPI master device clock frequency	–	50	MHz
F_{SPI_REF_CLK}	SPI reference clock frequency	–	200	MHz
SPI Slave Interface
T_SSPISSSCLK	Slave select asserted to first active clock edge	2	–	F_{SPI_REF_CLK} cycles
T_SSPISCLKSS	Last active clock edge to slave select deasserted	2	–	F_{SPI_REF_CLK} cycles
T_SSPIDCK	Input setup time for MOSI	5.0	–	ns
T_SSPICKD	Input hold time for MOSI	1	–	F_{SPI_REF_CLK} cycles
T_SSPICKO	MISO clock to out delay	0.0	13.0	ns
F_SSPICLK	SPI slave mode device clock frequency	–	25	MHz
F_{SPI_REF_CLK}	SPI reference clock frequency	–	200	MHz
The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 30 pF load. Valid when two SPI_REF_CLK delays are programmed between CS and CLK for T_MSPISSSCLK, and between CLK and CS for T_MSPISCLKSS in the SPI delay_reg0 register.