Revision History

In Table 1 and Table 1, updated description of V_CCO and added note about V_IN for POR_OVERRIDE pin.

Updated Table 1 for XAZU3T and XCZU3T.

Updated Note 7 in Table 2, and Note 10 in Table 4.

Updated Table 1, Table 1, and Table 1 to production release the XAZU3TEG devices in the -1Q, -1I, and -1LI speed/temperature grades and in Vivado Design Suite 2023.2.1 v1.06.

Updated DDR4 performance in SBVA484, UBVA494, and UBVA530 packages in Table 1.

Updated Note 2 in Table 1.

Updated Table 1, Table 1, and Table 1 to production release the XCZU3TCG and XCZU3TEG devices in the -2E, -2I, -1E, -1I, -2LE, and -1LI speed/temperature grades and in Vivado Design Suite 2023.1.2 v1.04.

Updated XCZU3T speed file data for this release in Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated the XCZU3T package skew values in Table 1.

Added note about Quad-SPI feedback clock MIO[6] pin to Table 1 and Table 2.

Replaced "die" with "rank" for LPDDR4 DRAM type in Table 3.

In Note 1 of Table 4, clarified that T_POR is T_POR,MAX.

Updated introductory paragraph in Available Speed Grades and Operating Voltages.

Added quiescent supply currents for XCZU1 to Table 1.

Added power-on currents for XCZU1 to Table 1.

Updated Table 1, Table 1, and Table 1 to production release the XCZU1CG and XCZU1EG devices in the -2E, -2I, -1E, -1I, -2LE, and -1LI speed/temperature grades and in Vivado Design Suite 2021.2.1 v1.29.

In Table 3, added UBVA494 and UBVA530 packages to all memory standards and note 6.

Updated XCZU1 speed file data for this release in Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated the XCZU1 package skew values in Table 1.

Updated T_SOL to add the UBVA530 package in Table 1.

For clarity, moved the location of the specifications for internal V_REF, differential termination, and temperature diode (ideality factor and series resistance) in Table 1.

Added the UBVA530 package to Table 5, Table 3, and other applicable tables.

Added Note 8 to Table 3: LPDDR3 quad die package devices are not supported.

Updated Note 7 in Table 1.

Added PS DDR I/O leakage current to I_L in Table 1.

Updated Table 1 to Vivado Design Suite 2020.1.1. The versions for XA, XC, and XQ devices changed. In Table 1, moved the XAZU7EV -1I (V_CCINT = 0.85V) and the XAZU11EG -1I (V_CCINT = 0.85V) to production. In Table 1, updated XAZU7EV and XAZU11EG production software and speed specification release version to Vivado tools 2020.1.1 v1.30.

To specify that the PS-GTR for PCI Express is only supported by the common clock architecture, added Note 1 to Table 5.

Edited Table 3 to refer to all speed grades in the SBVA484 and SFRA484 packages.

Removed the XAZU7EV and XAZU11EG in the -1LI (V_CCINT = 0.72V) speed/temperature grades because they were incorrectly added in the previous version. The XAZU7EV and XAZU11EG in the -1I speed/temperature grade was moved back to advance in Table 1 and Table 1. Updated Table 1 to Vivado Design Suite 2019.2.2 v1.27.

Added Note kpn1500674155216.html#kpn1500674155216__li_plio_diffio_mipi_dphy_mpsoc to Table 4. Revised symbol and description of IOPLL_TO_FPD maximum frequency in Table 5.

Increased the maximum line rate of the QPLL0 -1 (V_CCINT = 0.85V) output divider 1 in Table 1 and updated Notes 2 and 3.

Added the production released XAZU7EV and XAZU11EG devices in the -1I (V_CCINT = 0.85V), -1Q (V_CCINT = 0.85V), and -1LI (V_CCINT = 0.72V) speed/temperature grades to Table 1, Table 1, and Table 1 in Vivado Design Suite 2019.1.1 v1.26.

Added Note kpn1500674155216.html#kpn1500674155216__li_plio_hpio_mipi_dphy_vihmin to Table 2. Added the capability for XC and XA devices designed using Vivado Design Suite v2019.1.1 or later to increase the performance of the MIPI PHY transmitter/receiver in Table 3.

Updated the devices listed in Table 1 to Vivado Design Suite 2019.1 v1.25.

Revised minimum PS DDR data rates for all I-grade devices in Table 3.

Updated Note 1 in Table 2.

Added -1Q and -1M to Note 4 in Table 6.

Removed PCI Express Gen4 support in Table 1.

Updated Notes 4 and 6 in Table 3.

Updated the Video Codec Performance table.

Added the production released XQZU5EV, XQZU7EV, and XQZU15EG devices in the -2I, -1I, -1M, and -1LI speed/temperature grades to Table 1, Table 1, and Table 1 in Vivado Design Suite 2018.2.2 v1.22.

Updated Note 3 in Table 1, Table 2, Table 3. Updated the V_IDIFF description in Table 1. In Table 1, revised the Supply Sensor Error T_j conditions to –55°C.

Added the SFRC784, FFRB900, FFRB1156, and FFRC1156 packages to Table 1, Table 1, Table 3, Table 5, and Table 1, and the Integrated Interface Block for Interlaken section.

Updated the speed grade notes in Table 6.

Add the XQZU5EV, XQZU7EV, and XQZU15EG devices to Table 1, Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, Table 2, and Table 1.

Updated Table 1, Table 1, and Table 1 to production release the XCZU4EG, XCZU4EV, XCZU5EG, XCZU5EV, XCZU6EG, XCZU7EG, XCZU7EV, and XCZU9EG devices in the -3E speed/temperature grade and in Vivado Design Suite 2018.2.1 v1.21.

In Table 2, added Note 5 to the LVDS RX DDR maximum data.

In Table 1, revised the calculated values from 322.223 to 322.266.

In Table 1, added Notes 1 and 2.

Updated Table 1, Table 1, and Table 1 to production release the XAZU4EV and XAZU5EV devices in the -1Q speed/temperature grade in Vivado Design Suite 2018.2 v1.20.

Updated Table 1, Table 1, and Table 1 to production release the XCZU11EG,XCZU15EG, XCZU17EG, and XCZU19EG devices in the -3E speed/temperature grade in Vivado Design Suite 2018.1 v1.19.

Added the XAZU4EV and XAZU5EV devices to many tables.

In Table 1, revised the V_{CCINT_VCU} specifications, added automotive (Q) temperature to T_J , and updated Note 5.

Added the -1Q note to Table 1, Table 2, and Table 3.

Updated Table 1, Table 1, and Table 1 to production for the following devices/speed/temperature grades in Vivado Design Suite 2017.4.1 v1.18.

XCZU4CG/XCZU4EG/XCZU4EV: -2LE and -1LI

XCZU5CG/XCZU5EG/XCZU5EV: -2LE and -1LI

XCZU7CG/XCZU7EG/XCZU7EV: -2LE and -1LI

XCZU11EG: -2LE and -1LI

XCZU4EV and XAZU5EV: -1LI

In Vivado Design Suite 2017.4 v1.17, the XAZU4EV and XAZU5EV devices in the -1I speed/temperature grade were production released.

Revised some of the -3E speed files in Table 1, Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated Table 1, Table 1, and Table 1 to production for the following devices/speed/temperature grades in Vivado Design Suite 2017.4 v1.17.

XCZU4CG/XCZU4EG/XCZU4EV: -2E, -2I, -1E, -1I

XCZU5CG/XCZU5EG/XCZU5EV: -2E, -2I, -1E, -1I

XCZU7CG/XCZU7EG/XCZU7EV: -2E, -2I, -1E, -1I

XCZU17EG: -2LE and -1LI

XCZU19EG: -2LE and -1LI

Revised the F_REFCLK descriptions in Table 1. Added values to Table 1. Revised the F_GTYQRANGE2 -1 speed grade minimum in Table 1.

In Table 1, corrected the minimum voltage for the PL System Monitor section. Added Note 4 to Table 1. Added Note 1 to Table 2.

Updated Table 1, Table 1, and Table 1 to production for the following devices/speed/temperature grades in Vivado Design Suite 2017.3.1 v1.16.

XCZU2CG/XCZU2EG: -2LE and -1LI

XCZU3CG/XCZU3EG: -2LE and -1LI

XCZU6CG/XCZU6EG: -2LE and -1LI

XCZU9CG/XCZU9EG: -2LE and -1LI

XCZU15EG: -2LE and -1LI

XAZU2EG/XAZU3EG: -1LI

Also updated speed file data for this release in Table 1, Table 2, Table 3, Table 1, and Table 2.

Added specifications for Quad-SPI device clock frequency operating at 40 MHz with loopback disabled to Table 1 and Table 2.

Corrected the speed file version in Table 1 and Table 1 for production release of XAZU2EG and XAZU3EG with -1I and -1Q speed/temperature ranges and the XCZU11EG: -2E, -2I, -1E, -1I to Vivado Design Suite 2017.3 v1.15.

In Table 1, because the voltages are covered in Table 1, removed the note on V_IN for I/O input voltage for HD I/O banks. Updated T_SOL by package in Table 1. In Table 1, updated V_{CCINT_VCU}. Added Note 2 to Table 1 and Table 3.

Added the XAZU2EG and XAZU3EG production devices in -1I and -1Q speed/temperature ranges using Vivado Design Suite 2017.3 v1.14.

In Table 1, Table 1, and Table 1, updated the XCZU11EG: -2E, -2I, -1E, -1I to production in Vivado Design Suite 2017.3 v1.14. Also updated speed file data for this release in Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated Table 1, Table 1, and Table 1 to production release for the following devices/speed/temperature grades in Vivado Design Suite 2017.2.1.

XCZU17EG: -2E, -2I, -1E, -1I

XCZU19EG: -2E, -2I, -1E, -1I

In Table 1, revised the minimum T_SDSDRDCK3 value. In Table 1, revised the T_{OUTBUF_DELAY_O_PAD} -2 (V_CCINT = 0.85V) values for DIFF_SSTL135_S, DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S.

Revised some of the -3E and -1LI/-2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, and Table 2.

Revised the Integrated Interface Block for Interlaken section.

Updated Table 1, Table 1, and Table 1 to production release for the following devices/speed/temperature grades in Vivado Design Suite 2017.2.

XCZU15EG: -2E, -2I, -1E, -1I

Updated Note 15 in Table 1 for clarity. Updated Table 1 to remove Note 3, Note 6, and the MIPI_DPHY_DCI_LP row. These changes are because the DCI and POD standards are not supported in HD I/O banks.

Added Note 5 to Table 3. Updated descriptions in Table 5. Revised the -3E and -1LI/-2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, and Table 2. Updated the F_MAX symbol names and values in Table 1. Added Note 1 to Table 1. Added Note 3 to Table 1.

Updated Table 1, Table 1, and Table 1 to production release for the following

devices/speed/temperature grades in Vivado Design Suite 2017.1.

XCZU2CG and XCZU2EG: –2E, -2I, -1E, -1I

XCZU3CG and XCZU3EG: –2E, -2I, -1E, -1I

XCZU6CG and XCZU6EG: –2E, -2I, -1E, -1I

XCZU9CG and XCZU9EG: –2E, -2I, -1E, -1I

Added -2E (V_CCINT = 0.85V) speed grade where applicable. Removed -3E speed grade from the XCZU2 and XCZU3 devices in Table 1 and where applicable.

In Table 1, updated values and Note 2. In Table 1, added or updated many of the notes. Updated Table 1 including the notes and added Note 6. Moved and updated Table 2. Added Table 3. Updated Table 1 and added Note 4. Updated Table 1 and added Note 1.

Revised V_ICM in Table 1. Updated Table 3 and removed Note 1. Added Table 4 and Table 5. Updated Table 6 and removed F_FTMCLK. Updated T_RFPSCLK in Table 1. Updated Note 1 in Table 4. Updated Table 1. Removed the PS NAND Memory Controller Interface section. Significant changes to Table 1 and removed Note 3. Significant changes to Table 2 and updated Note 1. Removed F_{TSU_REF_CLK} from Table 1. Revised Table 1 and added Note 2 and Note 3. Revised Table 1 and added Note 2 and Note 3. Updated Table 1. Updated Table 1 and removed Note 2. Revised Table 1. Revised many of the tables in the PS-GTR Transceiver section. Revised Table 1 and Table 2. Removed Note 8 from Table 5.

Updated the values in Table 1, Table 1, Table 1, Table 1 Table 1, Table 2, Table 3, Table 1, and Table 2 to the Vivado Design Suite 2017.1 speed specifications.

Updated the values in Table 1 and Table 1. Added values to Table 3. Updated Table 1. Revised D_VPPOUT in Table 1. Update the values in Table 3. Added Note 6 to Table 6. Updated Table 7 and Table 8. Revised D_VPPOUT in Table 1. Updated the values in Table 3. In Table 1 updated the -1 (0.85V) specifications and removed Note 1. In Table 6 updated the -1 (0.85V) specifications and added Note 6. In Table 7 and Table 8, added the 28.21 jitter tolerance values and revised the notes. Revised the Integrated Interface Block for Interlaken and Integrated Interface Block for 100G Ethernet MAC and PCS sections. Revised the Configuration Switching Characteristics section. Removed the eFUSE Programming Conditions table and added the specifications to Table 1 and Table 1.

Updated some of the maximum voltages in the Processor System (PS) section and other specifications in the Programmable Logic (PL) and GTH or GTY Transceiver sections of Table 1. Updated Table 1, Table 1, Table 1, Table 3, and Table 1. Revised the Power Supply Sequencing section including Table 1. Added PS and VCU ramp times to Table 2. Revised V_ODIFF in Table 1. Updated Table 1. Added Note 1 to Table 1. Table 1 replaces the previous three PS memory performance tables. Added values to Table 1,Table 4, and Table 5. Deleted the waveforms in the PS Switching Characteristics section (Figures 1-16 and Figures 25-26). Revised values in the PS NAND Memory Controller Interface section. Added and updated data in Table 2. Added Note 3 to Table 1. Added Note 3 to Table 2. Added Note 1 to Table 1. Updated Table 1 and removed Note 3. Added data to Table 1. Updated Table 5. Added Table 6. Updated Table 8. Revised Table 1. Added data to Table 1. Added Note 2 to Table 2. Updated Table 5 and added Note 4. Updated V_L and V_H values in Table 1. Added T_{MINPER_CLK}, revised F_REFCLK, and Note 1 to Table 1. Added MMCM_F_{DPRCLK_MAX} to Table 1 and PLL_F_{DPRCLK_MAX} to Table 1. Added data to Table 1, Table 3, Table 2, Table 5, and updated the note references in Table 6. Updated Table 7 and added Note 8. Updated Table 8 and added Note 7. Added more protocols, Note 1 and Note 2 to Table 1. Removed the GTH Transceiver Protocol Jitter Characteristics section because it is covered in Table 1. Added Note 1 to Table 1. Added data to Table 1, Table 3, Table 2, Table 5. Added Note 2 to Table 4. Added note references in Table 6. Updated Table 7 and added Note 8. Updated Table 8 and added Note 7. Added more protocols and Note 3 to Table 1. Removed the GTY Transceiver Protocol Jitter Characteristics section because it is covered in Table 1. Revised Table 1. Added T_POR and updated F_ICAPCK in Table 1. Updated the Automotive Applications Disclaimer.

Updated the Summary description. In Table 1, revised V_IN for HP I/O banks and added clarifications to some descriptions and symbols. Added I_RPU, I_RPD, and Note 4 to Table 1 and updated V_{PS_MGTRAVCC}, the PL System Monitor section, and Note 3 and Note 5. Updated Note 5 in Table 1. Updated the PS Power-On/Off Power Supply Sequencing section including all the voltage supply names. Added MIPI_DPHY_DCI to Table 1, Table 2, and Table 4. Updated Table 1, including removing the V_CCO specification and adding Note 1. Added Note 1 to Table 1. Updated Table 1 speed specifications for Vivado Design Suite 2016.1. Added values to Table 1. Updated the -2 value in Table 2. Added F_DPLIVEVIDEO and updated F_FCIDMACLK in Table 6. Added VCO frequencies to Table 3. Added the T_PSPOR minimum to Table 4 and updated Note 1. Added Table 5. Added value delineation over V_CCINT operating voltages in Table 1. Revised values for F_TCK and T_TAPTCK/T_TCKTAP in Table 2 and added value delineation over V_CCINT operating voltages. Updated the PS NAND Memory Controller Interface section. Revised some units and Note 1 in Table 1 and Table 2. Removed Figure 6: Quad-SPI Interface (Feedback Clock Disabled) Timing. Updated Note 1 of Table 1. Added F_{TSI_REF_CLK} to Table 1 and updated Note 1. In Table 1, revised T_DCSDHSCLK1, T_DCSDHSCLK2, and T_DCSDHSCLK3 and Note 1. In Table 1, revised Note 1. In Table 1, revised Note 1. Revised Table 1, including Note 1, and added Note 2 and Note 3. In Table 1, Table 1, Table 1, and Table 1, revised Note 1. Updated Table 2. Replaced Table 5. Updated Table 1 and Table 1. Updated Table 1 and Table 1. In Table 1, added the Block RAM and FIFO Clock-to-Out Delays section. Updated the R_IN and C_EXT values in Table 2 and Table 2. Updated the -2 (0.72V) and -1 (0.72V) values and added Note 1 to Table 1. Added Table 4 and Table 4. Added Note 2 to Table 1. Revised data in Table 1. Revised Table 6. Revised data and added notes in the Integrated Interface Block for Interlaken section and Table 1. Moved Table 1. Revised INL in Table 1. Added notes to Table 1 and Table 2. In the eFUSE and Programming Conditions table, updated the I_PSFS description.