UltraRAM Switching Characteristics

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)

Document ID: DS925
Release Date: 2023-12-26
Revision: 1.26 English

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Zynq UltraScale+ MPSoCs that include this memory.

Table 1. UltraRAM Switching Characteristics
Symbol	Description	Speed Grade and V_CCINT Operating Voltages					Units
		0.90V	0.85V		0.72V
		-3	-2	-1	-2	-1
Maximum Frequency
F_MAX	UltraRAM maximum frequency with OREG_B = True	650	600	575	500	481	MHz
F_{MAX_ECC_NOPIPELINE}	UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = True	435	400	386	312	303	MHz
F_{MAX_NOPIPELINE}	UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = False	528	500	478	404	389	MHz
T_PW ¹	Minimum pulse width	650	700	730	800	832	ps
T_RSTPW	Asynchronous reset minimum pulse width. One cycle required	1 clock cycle
The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.