| Symbol | Description | Speed Grade and VCCINT Operating Voltages | Units | |||
|---|---|---|---|---|---|---|
| 0.85V | 0.72V | |||||
| -2 | -1 | -2 | -1 | |||
| PL Power-up Timing Characteristics | ||||||
| TPL | PS_PROG_B PL latency | 7.5 | 7.5 | 7.5 | 7.5 | ms, Max |
| Power-on reset from PL power-on to PL ready to configure (40 ms ramp rate time) | 65 | 65 | 65 | 65 | ms, Max | |
| 0 | 0 | 0 | 0 | ms, Min | ||
| Power-on reset from PL power-on to PL ready to configure with POR override (2 ms ramp rate time) | 15 | 15 | 15 | 15 | ms, Max | |
| 5 | 5 | 5 | 5 | ms, Min | ||
| TPS_PROG_B | PL program pulse width | 250 | 250 | 250 | 250 | ns, Min |
| Internal Configuration Access Port | ||||||
|
FICAPCK |
Internal configuration access port (ICAPE3) | 200 | 200 | 150 | 150 | MHz, Max |
| DNA Port Switching | ||||||
| FDNACK | DNA port frequency (DNA_PORT) | 200 | 200 | 175 | 175 | MHz, Max |
| STARTUPE3 Ports | ||||||
| FCFGMCLK | STARTUPE3 CFGMCLK output frequency | 50.00 | 50.00 | 50.00 | 50.00 | MHz, Typ |
| FCFGMCLKTOL | STARTUPE3 CFGMCLK output frequency tolerance | ±15 | ±15 | ±15 | ±15 | %, Max |
| TDCI_MATCH | Specifies a stall in the startup cycle until the digitally controlled impedance (DCI) match signals are asserted | 4 | 4 | 4 | 4 | ms, Max |
|
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