Device Pin-to-Pin Input Parameter Guidelines

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
Document ID
DS926
Release Date
2023-05-16
Revision
1.12 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSFD_ZU21 Global clock input and input flip-flop (or latch) without MMCM Setup XCZU21 0.81 0.83 1.68 1.83 ns
TPHFD_ZU21 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU25 Setup XCZU25 0.57 0.57 1.39 1.52 ns
TPHFD_ZU25 Hold 0.79 0.88 0.39 0.39 ns
TPSFD_ZU27 Setup XCZU27 0.81 0.83 1.68 1.83 ns
TPHFD_ZU27 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU28 Setup XCZU28 0.81 0.83 1.68 1.83 ns
TPHFD_ZU28 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU29 Setup XCZU29 0.81 0.83 1.68 1.83 ns
TPHFD_ZU29 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU39 Setup XCZU39 0.81 N/A 1.68 N/A ns
TPHFD_ZU39 Hold 0.64 N/A 0.22 N/A ns
TPSFD_ZU42 Setup XCZU42 1.93 2.08 1.93 2.08 ns
TPHFD_ZU42 Hold 0.49 0.49 0.04 0.04 ns
TPSFD_ZU43 Setup XCZU43 0.81 0.83 1.69 1.83 ns
TPHFD_ZU43 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU46 Setup XCZU46 0.81 0.83 1.69 1.83 ns
TPHFD_ZU46 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU47 Setup XCZU47 0.81 0.83 1.69 1.83 ns
TPHFD_ZU47 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU48 Setup XCZU48 0.81 0.83 1.69 1.83 ns
TPHFD_ZU48 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU49 Setup XCZU49 0.81 0.83 1.69 1.83 ns
TPHFD_ZU49 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_ZU63 Setup XCZU63 1.92 2.08 1.92 2.08 ns
TPHFD_ZU63 Hold 0.49 0.49 0.04 0.04 ns
TPSFD_ZU64 Setup XCZU64 1.92 2.08 1.92 2.08 ns
TPHFD_ZU64 Hold 0.49 0.49 0.04 0.04 ns
TPSFD_ZU65 Setup XCZU65 1.92 2.08 1.92 2.08 ns
TPHFD_ZU65 Hold 0.49 0.49 0.04 0.04 ns
TPSFD_ZU67 Setup XCZU67 1.92 2.08 1.92 2.08 ns
TPHFD_ZU67 Hold 0.49 0.49 0.04 0.04 ns
TPSFD_XQZU21 Setup XQZU21 0.81 0.83 N/A 1.83 ns
TPHFD_XQZU21 Hold 0.64 0.69 N/A 0.22 ns
TPSFD_XQZU28 Setup XQZU28 0.81 0.83 N/A 1.83 ns
TPHFD_XQZU28 Hold 0.64 0.69 N/A 0.22 ns
TPSFD_XQZU29 Setup XQZU29 0.81 0.83 N/A 1.83 ns
TPHFD_XQZU29 Hold 0.64 0.69 N/A 0.22 ns
TPSFD_XQZU48   Setup XQZU48 0.81 0.83 1.69 1.83 ns
TPHFD_XQZU48 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_XQZU49 Setup XQZU49 0.81 0.83 1.69 1.83 ns
TPHFD_XQZU49 Hold 0.64 0.69 0.22 0.22 ns
TPSFD_XQZU65 Setup XQZU65 1.92 2.08 1.92 2.08 ns
TPHFD_XQZU65 Hold 0.49 0.49 0.04 0.04 ns
TPSFD_XQZU67 Setup XQZU67 1.92 2.08 1.92 2.08 ns
TPHFD_XQZU67 Hold 0.49 0.49 0.04 0.04 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 2. Global Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSMMCMCC_ZU21 Global clock input and input flip-flop (or latch) with MMCM Setup XCZU21 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU21 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU25 Setup XCZU25 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU25 Hold –0.11 –0.11 –0.20 –0.20 ns
TPSMMCMCC_ZU27 Setup XCZU27 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU27 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU28 Setup XCZU28 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU28 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU29 Setup XCZU29 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU29 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU39 Setup XCZU39 1.95 N/A 1.95 N/A ns
TPHMMCMCC_ZU39 Hold –0.09 N/A –0.18 N/A ns
TPSMMCMCC_ZU42 Setup XCZU42 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_ZU42 Hold –0.08 –0.08 –0.08 –0.08 ns
TPSMMCMCC_ZU43 Setup XCZU43 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU43 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU46 Setup XCZU46 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU46 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU47 Setup XCZU47 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU47 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU48 Setup XCZU48 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU48 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU49 Setup XCZU49 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_ZU49 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_ZU63 Setup XCZU63 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_ZU63 Hold –0.08 –0.08 –0.08 –0.08 ns
TPSMMCMCC_ZU64 Setup XCZU64 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_ZU64 Hold –0.08 –0.08 –0.08 –0.08 ns
TPSMMCMCC_ZU65 Setup XCZU65 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_ZU65 Hold –0.08 –0.08 –0.08 –0.08 ns
TPSMMCMCC_ZU67 Setup XCZU67 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_ZU67 Hold –0.08 –0.08 –0.08 –0.08 ns
TPSMMCMCC_XQZU21 Setup XQZU21 1.95 2.09 N/A 2.09 ns
TPHMMCMCC_XQZU21 Hold –0.09 –0.09 N/A –0.18 ns
TPSMMCMCC_XQZU28 Setup XQZU28 1.95 2.09 N/A 2.09 ns
TPHMMCMCC_XQZU28 Hold –0.09 –0.09 N/A –0.18 ns
TPSMMCMCC_XQZU29 Setup XQZU29 1.95 2.09 N/A 2.09 ns
TPHMMCMCC_XQZU29 Hold –0.09 –0.09 N/A –0.18 ns
TPSMMCMCC_XQZU48   Setup XQZU48 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_XQZU48 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_XQZU49 Setup XQZU49 1.95 2.09 1.95 2.09 ns
TPHMMCMCC_XQZU49 Hold –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_XQZU65 Setup XQZU65 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_XQZU65 Hold –0.08 –0.08 –0.08 –0.08 ns
TPSMMCMCC_XQZU67 Setup XQZU67 1.99 2.14 1.99 2.14 ns
TPHMMCMCC_XQZU67 Hold –0.08 –0.08 –0.08 –0.08 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 3. Sampling Window
Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
TSAMP_BUFG 1 610 610 610 610 ps
TSAMP_NATIVE_DPA 2 100 125 125 150 ps
TSAMP_NATIVE_BISC 3 60 85 85 110 ps
  1. This parameter indicates the total sampling error of the Zynq UltraScale+ RFSoC DDR input registers, measured across voltage, temperature, and process. The measurement methodology uses the MMCM to capture the edges of operation of the DDR input registers. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
  2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.
  3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).
Table 4. Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)
Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
TINPUT_LOGIC_UNCERTAINTY 1 40 ps
TCAL_ERROR 2 24 ps
  1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or ISERDESE3).
  2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance.