Package Parameter Guidelines

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID

DS926

Release Date

2023-05-16

Revision

1.12 English

The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows.

Table 1. Package Skew
Symbol	Description	Device	Package	Value	Units
PKGSKEW	Package Skew^{1, 2}	XCZU21DR	FFVD1156	156	ps
		XCZU25DR	FFVE1156	145	ps
			FSVE1156	145	ps
			FFVG1517	165	ps
			FSVG1517	165	ps
		XCZU27DR	FFVE1156	145	ps
			FSVE1156	145	ps
			FFVG1517	165	ps
			FSVG1517	165	ps
		XCZU28DR	FFVE1156	145	ps
			FSVE1156	145	ps
			FFVG1517	165	ps
			FSVG1517	165	ps
		XCZU29DR	FFVF1760	160	ps
		XCZU29DR	FSVF1760	160	ps
		XCZU39DR	FFVF1760	160	ps
		XCZU39DR	FSVF1760	160	ps
		XCZU42DR	FFVE1156	148	ps
		XCZU42DR	FSVE1156	148	ps
		XCZU43DR	FFVE1156	145	ps
			FSVE1156	145	ps
			FFVG1517	148	ps
			FSVG1517	148	ps
		XCZU46DR	FFVH1760	131	ps
		XCZU46DR	FSVH1760	131	ps
		XCZU47DR	FFVE1156	145	ps
			FSVE1156	145	ps
			FFVG1517	148	ps
			FSVG1517	148	ps
		XCZU48DR	FFVE1156	145	ps
			FSVE1156	145	ps
			FFVG1517	148	ps
			FSVG1517	148	ps
		XCZU49DR	FFVF1760	158	ps
		XCZU49DR	FSVF1760	158	ps
		XCZU63DR	FFVE1156	148	ps
		XCZU63DR	FSVE1156	148	ps
		XCZU64DR	FFVE1156	148	ps
		XCZU64DR	FSVE1156	148	ps
		XCZU65DR	FFVE1156	148	ps
		XCZU65DR	FSVE1156	148	ps
		XCZU67DR	FFVE1156	148	ps
		XCZU67DR	FSVE1156	148	ps
		XQZU21DR	FFRD1156	168	ps
		XQZU28DR	FFRE1156	145	ps
		XQZU28DR	FFRG1517	164	ps
		XQZU29DR	FFRF1760	160	ps
		XQZU48DR	FFRE1156	143	ps
		XQZU48DR	FSRG1517	149	ps
		XQZU49DR	FSRF1760	157	ps
		XQZU65DR	FFRE1156	150	ps
		XQZU67DR	FFRE1156	148	ps
These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. Package delay information is available for these device/package combinations. This information can be used to deskew the package.