|Date||Version||Description of Revisions|
Updated introductory paragraph in Integrated Interface Block for PCI Express Designs.
Removed mention of I/Os being tristated at power-on from PS Power-On/Off Power Supply Sequencing.
Replaced "die" with "rank" for LPDDR4 DRAM type in Table 3.
Updated to PCIe Gen1, 2, 3, 4 protocol in Table 1.
Clarified low-power devices that support only one VCCINT voltage in Summary.
Added -1M to sample rate conditions in Table 4.
Added the production released XCZU42DR, XCZU65DR, and XCZU67DR devices to Table 1, Table 1, and Table 1 in Vivado Design Suite 2021.2.1 v1.29, and where applicable in other sections of this data sheet.
For clarity, moved the location of the specifications for internal VREF, differential termination, and temperature diode (ideality factor and series resistance) in Table 1.
Added RX Sync and TX Sync parameters to Table 3.
Added notes for full scale range and ADC bandwidth to Table 3.
Added DC coupling row to output current range and updated note about variable output power effective dynamic range in Table 3.
Added DFE Integrated Blocks.
|4/06/2021||1.8||Added package skews for the XQZU4xDR devices in Table 1. Added DAC maximum sample rate specification with clock forwarding feature to -2 device in Table 3. Updated Note 4 in Table 3.|
|4/01/2021||1.7||Added the production released XQZU48DR and
XQZU49DR to Table 1, Table 1, and
Table 1 in Vivado Design Suite 2020.2.2 v1.32, and where
applicable in other sections of this data sheet.
Added E/I and M speed grade rows to SFDR in Table 6.
Reduced the maximum sample rate in RF-DAC Electrical Characteristics.
Added the production released XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR, and XCZU49DR devices to Table 1, Table 1, and Table 1 in Vivado Design Suite 2020.2 v1.30, and where applicable in other sections of this data sheet.
Revised the Summary to include specific voltages by device.
Revised symbol and description of IOPLL_TO_FPD maximum frequency in Table 5.
Added the capability for XC devices designing with Vivado Design Suite v2019.1.1 or later to increase the performance of the MIPI PHY transmitter/receiver in Table 3.Updated Note 1 in Table 3
Added the RF-ADC/RF-DAC to PL Interface Switching Characteristics section.
Reorganized the Integrated RF-ADC Block and Integrated RF-DAC Block sections and the notes where the typical values are now specified at 40°C. Updated the typical Return Loss conditions and notes in each section. In the RF-ADC Electrical Characteristics section, Table 3, updated the common mode voltage descriptions. Clarified the meaning of all of the OIS parameter descriptions in the RF-ADC Performance Characteristics section. Updated the sampling rate Note 1 and revised the sample FREF to 250 MHz in Table 1, Table 2, and Table 7.
Added Table 5.
Production released the XCZU39DR device in -2I (VCCINT = 0.85V) and -2LI (VCCINT = 0.72V) speed/temperature grades throughout the data sheet for Vivado Design Suite 2019.1 v1.23
In the Integrated Interface Block for Interlaken section, removed package-specific limitation.
This version also adds the ruggedized FFRD1156 and FFRF1760 packages to support the XQZU21DR and XQZU29DR.
Updated Table 1 to Vivado Design Suite 2018.3.1 v1.23.
Added LVDS component mode notes to Programmable Logic (PL) Performance Characteristics.
Table 1, revised the Supply Sensor Error Tj conditions to –55°C.
Updated the speed grade notes in Table 6.
In Table 1, removed Note 1.
Removed PCI Express Gen4 support in Table 1 and Note 1, Note 2, and Note 3.
In Table 1, added M-grade NSD FIN = 3.5 GHz, the HD3 FIN = 2.4 GHz, and IM3 FIN = 3.5 GHz, F1, F2 at –7 dBFS and 20 MHz delta.
In Table 1, added M-grade ACLR FC = 3.5 GHz.
In Table 3, added M-grade ACLR FC = 240 MHz, and NSD FOUT = 3.5 GHz CW at –10 dBFS.
Added the MTS sync specification to Table 1.
Where applicable, added the -2LI (VCCINT = 0.72V) speed/temperature grade specifications throughout this data sheet. Updated Table 1, Table 1, and Table 1 to production for the following devices/speed/temperature grades in Vivado Design Suite 2018.2.1 v1.21.
XCZU21DR: -1LI (VCCINT = 0.85V), and -2LI, -1LI (VCCINT = 0.72V)
XCZU25DR: -1LI (VCCINT = 0.85V), and -2LI, -1LI (VCCINT = 0.72V)
XCZU27DR: -1LI (VCCINT = 0.85V), and -2LI, -1LI (VCCINT = 0.72V)
XCZU28DR: -1LI (VCCINT = 0.85V), and -2LI, -1LI (VCCINT = 0.72V)
XCZU29DR: -1LI (VCCINT = 0.85V), and -2LI, -1LI (VCCINT = 0.72V)
In Table 2, added RF-DAC, RF-ADC, and SD-FEC power supply values.
In Table 2, added -2LI.
In Table 1, revised the calculated values from 322.223 to 322.266. Added Note 1.
Edited Note 2 in Table 1.
In Table 1, added Notes 1 and 2.
|6/18/2018||1.1||Updated the RF-ADC, RF-DAC, and
SD-FEC section in Absolute Maximum Ratings including
. Revised Note 14 in
Table 1. Added ADC_REXT
to DC Characteristics Over Recommended Operating Conditions. In Table 1, clarified the VCCO_PSIO descriptions.
Added the RF-DAC/RF-ADC power supply sequencing information to the PL Power-On/Off Power Supply Sequencing section.
XCZU21DR: -2E, -2I, -2LE, -1E, -1I (VCCINT = 0.85V), and -2LE (VCCINT = 0.72V)
XCZU25DR: -2E, -2I, -2LE, -1E, -1I (VCCINT = 0.85V), and -2LE (VCCINT = 0.72V)
XCZU27DR: -2E, -2I, -2LE, -1E, -1I (VCCINT = 0.85V), and -2LE (VCCINT = 0.72V)
XCZU28DR: -2E, -2I, -2LE, -1E, -1I (VCCINT = 0.85V), and -2LE (VCCINT = 0.72V)
XCZU29DR: -2E, -2I, -2LE, -1E, -1I (VCCINT = 0.85V), and -2LE (VCCINT = 0.72V)
Added Table 1.
|4/09/2018||1.0||Initial AMD release.|