Clock Buffers and Networks

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. Clock Buffers Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Global Clock Switching Characteristics (Including BUFGCTRL)
FMAX Maximum frequency of a global clock tree (BUFG) 775 667 667 MHz
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV)
FMAX Maximum frequency of a global clock buffer with input divide capability (BUFGCE_DIV) 775 667 667 MHz
Global Clock Buffer with Clock Enable (BUFGCE)
FMAX Maximum frequency of a global clock buffer with clock enable (BUFGCE) 775 667 667 MHz
Leaf Clock Buffer with Clock Enable (BUFCE_LEAF)
FMAX Maximum frequency of a leaf clock buffer with clock enable (BUFCE_LEAF) 775 667 667 MHz
GTH or GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT)
FMAX Maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability 512 512 512 MHz