Configuration Switching Characteristics

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. Configuration Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Power-up Timing Characteristics
TPL Program latency 7.5 7.5 7.5 ms, Max
TPOR Power-on reset (40 ms maximum ramp rate) 65 65 65 ms, Max
0 0 0 ms, Min
Power-on reset with POR override (2 ms maximum ramp rate) 15 15 15 ms, Max
5 5 5 ms, Min
TPROGRAM Program pulse width 250 250 250 ns, Min
CCLK Output (Master Mode)
TICCK Master CCLK output delay from INIT_B 150 150 150 ns, Min
TMCCKL 1 Master CCLK clock Low time duty cycle 40/60 40/60 40/60 %, Min/Max
TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 %, Min/Max
FMCCK Master SPI (x1/x2/x4)

CCLK frequency

150 150 125 MHz, Max
Master SPI (x8) or Master BPI (x8/x16) 2

CCLK frequency

150 150 125
FMCCK_START Master CCLK frequency at start of configuration 2.70 2.70 2.70 MHz, Typ
FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK ±15 ±15 ±15 %, Max
CCLK Input (Slave Mode)
TSCCKL Slave CCLK clock minimum Low time 2.5 2.5 2.5 ns, Min
TSCCKH Slave CCLK clock minimum High time 2.5 2.5 2.5 ns, Min
FSCCK Slave serial CCLK frequency 125 125 125 MHz, Max
Slave SelectMAP CCLK frequency 125 125 125
EMCCLK Input (Master Mode)
TEMCCKL External master CCLK Low time 2.5 2.5 2.5 ns, Min
TEMCCKH External master CCLK High time 2.5 2.5 2.5 ns, Min
FEMCCK External master CCLK frequency with Master SPI x1/x2/x4 150 150 125 MHz, Max
External master CCLK frequency with Master SPI x8 or Master BPI x8/x16 2 150 150 125
Internal Configuration Access Port
FICAPCK Internal configuration access port (ICAPE3) 200 200 150 MHz, Max
Slave Serial Mode Programming Switching
TDCCK/TCCKD DIN setup/hold 3.0/0 3.0/0 4.0/0 ns, Min
TCCO DOUT clock to out 8.0 8.0 9.0 ns, Max
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD D[31:00] setup/hold 3.5/0 3.5/0 4.5/0 ns, Min
TSMCSCCK/TSMCCKCS CSI_B setup/hold 4.0/0 4.0/0 5.0/0 ns, Min
TSMWCCK/TSMCCKW RDWR_B setup/hold 10.0/0 10.0/0 11.0/0 ns, Min
TSMCKCSO CSO_B clock to out (330Ω pull-up resistor required) 7.0 7.0 7.0 ns, Max
TSMCO D[31:00] clock to out in readback 8.0 8.0 8.0 ns, Max
FRBCCK Readback frequency 125 125 125 MHz, Max
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP TMS and TDI setup/hold 3.0/2.0 3.0/2.0 3.0/2.0 ns, Min
TTCKTDO TCK falling edge to TDO output 7.0 7.0 7.0 ns, Max
FTCK TCK frequency 66 66 66 MHz, Max
BPI Master Flash Mode Programming Switching
TBPICCO A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out 10 10 10 ns, Max
TBPIDCC/TBPICCD D[15:00] setup/hold 3.5/0 3.5/0 4.5/0 ns, Min
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPICCD D[03:00] setup/hold 3.0/0 3.0/0 4.0/0 ns, Min
TSPIDCC/TSPICCD D[07:04] setup/hold 3.5/0 3.5/0 4.5/0 ns, Min
TSPICCM MOSI clock to out 8.0 8.0 8.0 ns, Max
TSPICCM2 D[04] clock to out 10.0 10.0 10.0 ns, Max
TSPICCFC FCS_B clock to out 8.0 8.0 8.0 ns, Max
TSPICCFC2 FCS2_B clock to out 10.0 10.0 10.0 ns, Max
DNA Port Switching
FDNACK DNA port frequency 200 200 175 MHz, Max
STARTUPE3 Ports
TUSRCCLKO STARTUPE3 USRCCLKO input port to CCLK pin output delay 0.25/6.50 0.25/7.50 0.25/9.00 ns, Min/Max
TDO DO[3:0] ports to D03-D00 pins output delay 0.25/7.70 0.25/8.40 0.25/10.00 ns, Min/Max
TDTS DTS[3:0] ports to D03-D00 pins 3-state delays 0.25/7.70 0.25/8.40 0.25/10.00 ns, Min/Max
TFCSBO FCSBO port to FCS_B pin output delay 0.25/7.50 0.25/8.40 0.25/9.80 ns, Min/Max
TFCSBTS FCSBTS port to FCS_B pin 3-state delay 0.25/7.50 0.25/8.40 0.25/9.80 ns, Min/Max
TUSRDONEO USRDONEO port to DONE pin output delay 0.25/9.40 0.25/10.50 0.25/12.10 ns, Min/Max
TUSRDONETS USRDONETS port to DONE pin 3-state delay 0.25/9.40 0.25/10.50 0.25/12.10 ns, Min/Max
TDI D03-D00 pins to DI[3:0] ports input delay 0.5/3.1 0.5/3.5 0.5/4.0 ns, Min/Max
FCFGMCLK STARTUPE3 CFGMCLK output frequency 50 50 50 MHz, Typ
FCFGMCLKTOL STARTUPE3 CFGMCLK output frequency tolerance ±15 ±15 ±15 %, Max
TDCI_MATCH Specifies a stall in the start-up cycle until the digitally controlled impedance (DCI) match signals are asserted 4 4 4 ms, Max
  1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this duty-cycle requirement.
  2. SPI mode is recommended for master mode configuration from flash memory because of the higher configuration rates and low configuration interface pin counts. Due to the obsolescence of synchronous read-mode flash devices, BPI mode performance is limited. For system configuration rates with SPI flash and parallel NOR flash in BPI asynchronous read mode see the UltraScale Architecture Configuration User Guide (UG570).