DC Characteristics Over Recommended Operating Conditions

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ 1 Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.68 V
VDRAUX Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 V
IREF VREF leakage current per pin 15 µA
CIN 3 Die input capacitance at the pad (HP I/O) 3.1 pF
Die input capacitance at the pad (HD I/O) 4.75 pF
IRPU Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V 75 190 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V 50 169 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V 60 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V 30 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V 10 100 µA
IRPD Pad pull-down (when selected) at VIN = 3.3V 60 200 µA
Pad pull-down (when selected) at VIN = 1.8V 29 120 µA
ICCADCON Analog supply current for the SYSMON circuits in the power-up state 8 mA
ICCADCOFF Analog supply current for the SYSMON circuits in the power-down state 1.5 mA
IBATT 4, 5 Battery supply current at VBATT = 1.89V 650 nA
Battery supply current at VBATT = 1.20V 150 nA
IPFS 6 VCCAUX additional supply current during eFUSE programming 115 mA
Internal VREF 50% VCCO VCCO x 0.49 VCCO x 0.50 VCCO x 0.51 V
70% VCCO VCCO x 0.69 VCCO x 0.70 VCCO x 0.71 V
Differential termination Programmable differential termination (TERM_100) for HP I/O banks –35% 100 +35% Ω
n Temperature diode ideality factor 1.026
r Temperature diode series resistance 2 Ω
Calibrated programmable on-die termination (DCI) in HP I/O banks 7 (measured per JEDEC specification)
R 9 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –10% 8 40 +10% 8 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –10% 8 48 +10% 8 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –10% 8 60 +10% 8 Ω
Programmable input termination to VCCO where ODT = RTT_40 –10% 8 40 +10% 8 Ω
Programmable input termination to VCCO where ODT = RTT_48 –10% 8 48 +10% 8 Ω
Programmable input termination to VCCO where ODT = RTT_60 –10% 8 60 +10% 8 Ω
Programmable input termination to VCCO where ODT = RTT_120 –10% 8 120 +10% 8 Ω
Programmable input termination to VCCOwhere ODT = RTT_240 –10% 8 240 +10% 8 Ω
Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification)
R 9 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –50% 40 +50% Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –50% 60 +50% Ω
Programmable input termination to VCCO where ODT = RTT_40 –50% 40 +50% Ω
Programmable input termination to VCCO where ODT = RTT_48 –50% 48 +50% Ω
Programmable input termination to VCCO where ODT = RTT_60 –50% 60 +50% Ω
Programmable input termination to VCCO where ODT = RTT_120 –50% 120 +50% Ω
Programmable input termination to VCCO where ODT = RTT_240 –50% 240 +50% Ω
Uncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification)
R 9 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω
  1. Typical values are specified at nominal voltage, 25°C.
  2. For the HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA.
  3. This measurement represents the die capacitance at the pad, not including the package.
  4. Maximum value specified for worst case process at 25°C.
  5. IBATT is measured when the battery-backed RAM (BBRAM) is enabled.
  6. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is active).
  7. VRP resistor tolerance is (240Ω ±1%).
  8. If VRP resides at a different bank (DCI cascade), the range increases to ±15%.
  9. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide (UG571).