FPGA Logic Performance Characteristics

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English

This section provides the performance characteristics of some common functions and designs implemented in the Artix UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics section.

In each of the following LVDS performance tables, the I/O bank type is either high performance (HP) or high density (HD).

In LVDS component mode:

  • For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades.
  • For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
  • For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
Table 1. LVDS Component Mode Performance
Description I/O Bank Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Min Max Min Max Min Max
LVDS TX DDR (OSERDES 4:1, 8:1) HP 0 1250 0 1250 0 1250 Mb/s
LVDS TX SDR (OSERDES 2:1, 4:1) HP 0 625 0 625 0 625 Mb/s
LVDS RX DDR (ISERDES 1:4, 1:8) 1 HP 0 1250 0 1250 0 1250 Mb/s
LVDS RX DDR HD 0 250 0 250 0 250 Mb/s
LVDS RX SDR (ISERDES 1:2, 1:4) 1 HP 0 625 0 625 0 625 Mb/s
LVDS RX SDR HD 0 125 0 125 0 125 Mb/s
  1. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.
Table 2. LVDS Native Mode Performance
Description 1, 2 DATA_WIDTH I/O Bank Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 3 -1 3 -1 3
Min Max Min Max Min Max
LVDS TX DDR (TX_BITSLICE) 4 HP 375 1600 375 1600 375 1260 Mb/s
8 375 1600 375 1600 375 1600 Mb/s
LVDS TX SDR (TX_BITSLICE) 4 HP 187.5 800 187.5 800 187.5 630 Mb/s
8 187.5 800 187.5 800 187.5 800 Mb/s
LVDS RX DDR (RX_BITSLICE) 4 4 HP 375 1600 5 375 1600 5 375 1260 5 Mb/s
8 375 1600 5 375 1600 5 375 1600 5 Mb/s
LVDS RX SDR (RX_BITSLICE) 4 4 HP 187.5 800 187.5 800 187.5 630 Mb/s
8 187.5 800 187.5 800 187.5 800 Mb/s
  1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface.
  2. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the minimum frequency is PLL_FVCOMIN/2.
  3. In the UBVA368 and SBVB484 packages, the maximum data rate is 1260 Mb/s for DDR interfaces and 630 Mb/s for SDR interfaces.
  4. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.
  5. Asynchronous receiver performance is limited to 1300 Mb/s for -2 speed grades and to 1250 Mb/s for -1 speed grades.
Table 3. MIPI D-PHY Performance
Description I/O Bank Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Maximum MIPI D-PHY transmitter or receiver data rate per lane HP 2500 2500 1260 Mb/s
All devices in UBVA368 and SBVB484 packages 1260 1260 1260 Mb/s
Table 4. LVDS Native-Mode 1000BASE-X Support
Description 1 I/O Bank Type Speed Grade and VCCINT Operating Voltages
0.85V 0.72V
-2 -1 -1
1000BASE-X HP Yes
  1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008).

The following table provides the maximum data rates for applicable memory standards using the Artix UltraScale+ FPGA memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale Architecture PCB Design User Guide (UG583), electrical analysis, and characterization of the system.

Table 5. Maximum Physical Interface (PHY) Rate for Memory Interfaces
Memory Standard Packages DRAM Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
DDR4

FFVB676 packages

Single rank component 2400 2133 1866 Mb/s
1 rank DIMM 1, 2 2133 1866 1600 Mb/s
2 rank DIMM 1, 3 1866 1600 1333 Mb/s
4 rank DIMM 1, 4 1333 N/A N/A Mb/s

SFVB784 packages

Single rank component 2400 2133 1866 Mb/s
1 rank DIMM 1, 2 2133 1866 1600 Mb/s
2 rank DIMM 1, 3 1866 1600 1333 Mb/s
4 rank DIMM 1, 4 1333 N/A N/A Mb/s
SBVB484 and UBVA368 packages Single rank component 1600 1600 1600 Mb/s
1 rank DIMM 1, 2 1333 1333 1333 Mb/s
2 rank DIMM 1, 3 1333 1333 N/A Mb/s
DDR3

FFVB676 packages

Single rank component 1866 1866 1600 Mb/s
1 rank DIMM 1, 2 1600 1600 1600 Mb/s
2 rank DIMM 1, 3 1600 1600 1333 Mb/s
4 rank DIMM 1, 4 1066 1066 800 Mb/s

SFVB784 packages

Single rank component 1866 1866 1600 Mb/s
1 rank DIMM 1, 2 1600 1600 1600 Mb/s
2 rank DIMM 1, 3 1600 1600 1333 Mb/s
4 rank DIMM 1, 4 1066 1066 800 Mb/s
SBVB484 and UBVA368 packages Single rank component 1600 1600 1333 Mb/s
1 rank DIMM 1, 2 1333 1333 1066 Mb/s
2 rank DIMM 1, 3 1333 1333 800 Mb/s
4 rank DIMM 1, 4 800 800 N/A Mb/s
DDR3L

FFVB676 packages

Single rank component 1600 1600 1600 Mb/s
1 rank DIMM 1, 2 1600 1600 1333 Mb/s
2 rank DIMM 1, 3 1333 1333 1066 Mb/s
4 rank DIMM 1, 4 800 800 606 Mb/s

SFVB784 packages

Single rank component 1600 1600 1600 Mb/s
1 rank DIMM 1, 2 1600 1600 1333 Mb/s
2 rank DIMM 1, 3 1333 1333 1066 Mb/s
4 rank DIMM 1, 4 800 800 606 Mb/s
SBVB484 and UBVA368 packages Single rank component 1333 1333 1066 Mb/s
1 rank DIMM 1, 2 1066 1066 800 Mb/s
2 rank DIMM 1, 3 800 800 606 Mb/s
4 rank DIMM 1, 4 N/A N/A N/A Mb/s
QDR II+ All Single rank component 5 633 600 550 MHz
QDR IV XP FFVB676 and SFVB784 packages Single rank component 1066 1066 933 MHz
SBVB484 and UBVA368 packages Single rank component 800 800 800 MHz
RLDRAM 3

FFVB676 packages

Single rank component 1066 1066 933 MHz
SFVB784 packages Single rank component 1066 933 800 MHz
SBVB484 and UBVA368 packages Single rank component 933 800 667 MHz
LPDDR3 FFVB676 Single rank component 1600 1600 1600 Mb/s
SFVB784 Single rank component 1600 1600 1600 Mb/s
SBVB484 and UBVA368 Single rank component 1600 1600 1600 Mb/s
  1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
  2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
  3. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
  4. Includes: 2 rank 2 slot, 4 rank 1 slot.
  5. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.