GTY Transceiver DC Input and Output Levels

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)
Document ID
DS931
Release Date
2023-12-26
Revision
1.6 English

Table 1 summarizes the DC specifications of the GTY transceivers in Artix UltraScale+ FPGAs. Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further details.

Table 1. GTY Transceiver DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPIN Differential peak-to-peak input voltage (external AC coupled) >10.3125 Gb/s 150 – 1250 mV
6.6 Gb/s to 10.3125 Gb/s 150 – 1250 mV
≤ 6.6 Gb/s 150 – 2000 mV
VIN Single-ended input voltage. Voltage measured at the pin referenced to GND. DC coupled VMGTAVTT = 1.2V –400 – VMGTAVTT mV
VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V – 2/3 VMGTAVTT – mV
DVPPOUT Differential peak-to-peak output voltage 1 Transmitter output swing is set to 11111 800 – – mV
VCMOUTDC Common mode output voltage: DC coupled (equation based) When remote RX is terminated to GND VMGTAVTT/2 – DVPPOUT/4 mV
When remote RX termination is floating VMGTAVTT – DVPPOUT/2 mV
When remote RX is terminated to VRX_TERM 2 mV
VCMOUTAC Common mode output voltage: AC coupled Equation based VMGTAVTT – DVPPOUT/2 mV
RIN Differential input resistance – 100 – Ω
ROUT Differential output resistance – 100 – Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew – – 10 ps
CEXT Recommended external AC coupling capacitor 3 – 100 – nF
  1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the UltraScale Architecture GTY Transceivers User Guide (UG578) and can result in values lower than reported in this table.
  2. VRX_TERM is the remote RX termination voltage.
  3. Other values can be used as appropriate to conform to specific protocols and standards.
Figure 1. Single-Ended Peak-to-Peak Voltage

Figure 2. Differential Peak-to-Peak Voltage

The following tables summarize the DC specifications of the clock input/output levels of the GTY transceivers in Artix UltraScale+ FPGAs. Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further details.

Table 2. GTY Transceiver Clock DC Input Level Specification
Symbol DC Parameter Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 250 – 2000 mV
RIN Differential input resistance – 100 – Ω
CEXT Required external AC coupling capacitor – 10 – nF
Table 3. GTY Transceiver Clock Output Level Specification
Symbol Description Conditions Min Typ Max Units
VOL Output Low voltage for P and N RT = 100Ω across P and N signals 100 – 330 mV
VOH Output High voltage for P and N RT = 100Ω across P and N signals 500 – 700 mV
VDDOUT Differential output voltage (P–N), P  =  High (N–P), N = High RT = 100Ω across P and N signals 300 – 430 mV
VCMOUT Common mode voltage RT = 100Ω across P and N signals 300 – 500 mV