GTY Transceiver Switching Characteristics

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English

Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further information.

Table 1. GTY Transceiver Performance
Symbol Description Output Divider Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
FGTYMAX GTY maximum line rate 16.375 1 16.375 1 12.5 Gb/s
FGTYMIN GTY minimum line rate 0.5 0.5 0.5 Gb/s
  Min Max Min Max Min Max  
FGTYCRANGE CPLL line rate range 2 1 4.0 12.5 4.0 8.5 4.0 8.5 Gb/s
2 2.0 6.25 2.0 4.25 2.0 4.25 Gb/s
4 1.0 3.125 1.0 2.125 1.0 2.125 Gb/s
8 0.5 1.5625 0.5 1.0625 0.5 1.0625 Gb/s
16 N/A Gb/s
32 N/A Gb/s
  Min Max Min Max Min Max  
FGTYQRANGE1 QPLL0 line rate range 3 1 9.8 16.375 9.8 16.375 9.8 12.5 Gb/s
2 4.9 8.1875 4.9 8.1875 4.9 8.1875 Gb/s
4 2.45 4.0938 2.45 4.0938 2.45 4.0938 Gb/s
8 1.225 2.0469 1.225 2.0469 1.225 2.0469 Gb/s
16 0.6125 1.0234 0.6125 1.0234 0.6125 1.0234 Gb/s
  Min Max Min Max Min Max  
FGTYQRANGE2 QPLL1 line rate range 4 1 16.0 16.375 16.0 16.375 N/A Gb/s
1 8.0 13.0 8.0 12.5 8.0 12.5 Gb/s
2 4.0 6.5 4.0 6.5 4.0 6.5 Gb/s
4 2.0 3.25 2.0 3.25 2.0 3.25 Gb/s
8 1.0 1.625 1.0 1.625 1.0 1.625 Gb/s
16 0.5 0.8125 0.5 0.8125 0.5 0.8125 Gb/s
  Min Max Min Max Min Max  
FCPLLRANGE CPLL frequency range 2.0 6.25 2.0 4.25 2.0 4.25 GHz
FQPLL0RANGE QPLL0 frequency range 9.8 16.375 9.8 16.375 9.8 16.375 GHz
FQPLL1RANGE QPLL1 frequency range 8.0 13.0 8.0 13.0 8.0 13.0 GHz
  1. GTY transceiver line rates are package limited: UBVA368, SBVB484, SFVB784 to 12.5 Gb/s.
  2. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider.
  3. The values listed are the rounded results of the calculated equation ( QPLL0_Frequency × RATE)/Output_Divider where RATE is 1 when QPLL0_CLKOUT_RATE is set to HALF and 2 if QPLL0_CLKOUT_RATE is set to FULL.
  4. The values listed are the rounded results of the calculated equation (QPLL1_Frequency × RATE)/Output_Divider where RATE is 1 when QPLL1_CLKOUT_RATE is set to HALF and 2 if QPLL1_CLKOUT_RATE is set to FULL.
Table 2. GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description All Speed Grades Units
FGTYDRPCLK GTYDRPCLK maximum frequency 250 MHz
Table 3. GTY Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range 60 820 MHz
TRCLK Reference clock rise time 20% – 80% 200 ps
TFCLK Reference clock fall time 80% – 20% 200 ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 %
Table 4. GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask
Symbol Description 1, 2 Offset Frequency Min Typ Max Units
QPLLREFCLKMASK QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 156.25 MHz 10 kHz –112 dBc/Hz
100 kHz –128
1 MHz –145
QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz –103 dBc/Hz
100 kHz –123
1 MHz –143
QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz –98 dBc/Hz
100 kHz –117
1 MHz –140
CPLLREFCLKMASK CPLL reference clock select phase noise mask at REFCLK frequency = 156.25 MHz 10 kHz –112 dBc/Hz
100 kHz –128
1 MHz –145
50 MHz –145
CPLL reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz –103 dBc/Hz
100 kHz –123
1 MHz –143
50 MHz –145
CPLL reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz –98 dBc/Hz
100 kHz –117
1 MHz –140
50 MHz –144
  1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
  2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol, e.g., PCIe.
Table 5. GTY Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions All Speed Grades Units
Min Typ Max
TLOCK Initial PLL lock. 1 ms
TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE) After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. 50,000 37 x 106 UI
Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled 50,000 2.3 x 106 UI
Table 6. GTY Transceiver User Clock Switching Characteristics
Symbol Description 1 Data Width Conditions (Bit) Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
Internal Logic Interconnect Logic -2 2 -1 3, 5 -1 4
FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 402.891 322.266 MHz
FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 402.891 322.266 MHz
FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from TXPROGDIVCLK 511.719 511.719 511.719 MHz
FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from RXPROGDIVCLK 511.719 511.719 511.719 MHz
FTXIN TXUSRCLK 6 maximum frequency 16 16, 32 511.719 390.625 322.266 MHz
32 32, 64 511.719 390.625 322.266 MHz
64 64, 128 255.859 255.859 195.313 MHz
20 20, 40 409.375 312.500 257.813 MHz
40 40, 80 409.375 312.500 257.813 MHz
80 80, 160 204.688 204.688 156.250 MHz
FRXIN RXUSRCLK 6 maximum frequency 16 16, 32 511.719 390.625 322.266 MHz
32 32, 64 511.719 390.625 322.266 MHz
64 64, 128 255.859 255.859 195.313 MHz
20 20, 40 409.375 312.500 257.813 MHz
40 40, 80 409.375 312.500 257.813 MHz
80 80, 160 204.688 204.688 156.250 MHz
FTXIN2 TXUSRCLK2 6 maximum frequency 16 16 511.719 390.625 322.266 MHz
16 32 255.859 195.313 161.133 MHz
32 32 511.719 390.625 322.266 MHz
32 64 255.859 195.313 161.133 MHz
64 64 255.859 255.859 195.313 MHz
64 128 127.930 127.930 97.656 MHz
20 20 409.375 312.500 257.813 MHz
20 40 204.688 156.250 128.906 MHz
40 40 409.375 312.500 257.813 MHz
40 80 204.688 156.250 128.906 MHz
80 80 204.688 204.688 156.250 MHz
80 160 102.344 102.344 78.125 MHz
FRXIN2 RXUSRCLK2 6 maximum frequency 16 16 511.719 390.625 322.266 MHz
16 32 255.859 195.313 161.133 MHz
32 32 511.719 390.625 322.266 MHz
32 64 255.859 195.313 161.133 MHz
64 64 255.859 255.859 195.313 MHz
64 128 127.930 127.930 97.656 MHz
20 20 409.375 312.500 257.813 MHz
20 40 204.688 156.250 128.906 MHz
40 40 409.375 312.500 257.813 MHz
40 80 204.688 156.250 128.906 MHz
80 80 204.688 204.688 156.250 MHz
80 160 102.344 102.344 78.125 MHz
  1. Clocking must be implemented as described in the UltraScale Architecture GTY Transceivers User Guide (UG578).
  2. For speed grades -2E and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s.
  3. For speed grades -1E, and -1I a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s.
  4. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when VCCINT = 0.85V or 5.15625 Gb/s when VCCINT = 0.72V.
  5. For the speed grades -1E and -1I, only a 64- or 80-bit internal data path can be used for line rates above 12.5 Gb/s.
  6. When the gearbox is used, these maximums refer to the XCLK. For more information, see the Valid Data Width Combinations for TX Asynchronous Gearbox table in the UltraScale Architecture GTY Transceivers User Guide (UG578).
Table 7. GTY Transceiver Transmitter Switching Characteristics
Symbol Description Condition Min Typ Max Units
FGTYTX Serial data rate range 0.500 FGTYMAX Gb/s
TRTX TX rise time 20%–80% 21 ps
TFTX TX fall time 80%–20% 21 ps
TLLSKEW TX lane-to-lane skew 1 500.00 ps
TJ16.375 Total jitter 2, 4 16.375 Gb/s 0.28 UI
DJ16.375 Deterministic jitter 2, 4 0.17 UI
TJ15.0 Total jitter 2, 4 15.0 Gb/s 0.28 UI
DJ15.0 Deterministic jitter 2, 4 0.17 UI
TJ14.1 Total jitter 2, 4 14.1 Gb/s 0.28 UI
DJ14.1 Deterministic jitter 2, 4 0.17 UI
TJ14.1 Total jitter 2, 4 14.025 Gb/s 0.28 UI
DJ14.1 Deterministic jitter 2, 4 0.17 UI
TJ13.1 Total jitter 2, 4 13.1 Gb/s 0.28 UI
DJ13.1 Deterministic jitter 2, 4 0.17 UI
TJ12.5_QPLL Total jitter 2, 4 12.5 Gb/s 0.28 UI
DJ12.5_QPLL Deterministic jitter 2, 4 0.17 UI
TJ12.5_CPLL Total jitter 3, 4 12.5 Gb/s 0.33 UI
DJ12.5_CPLL Deterministic jitter 3, 4 0.17 UI
TJ11.3_QPLL Total jitter 2, 4 11.3 Gb/s 0.28 UI
DJ11.3_QPLL Deterministic jitter 2, 4 0.17 UI
TJ10.3125_QPLL Total jitter 2, 4 10.3125 Gb/s 0.28 UI
DJ10.3125_QPLL Deterministic jitter 2, 4 0.17 UI
TJ10.3125_CPLL Total jitter 3, 4 10.3125 Gb/s 0.33 UI
DJ10.3125_CPLL Deterministic jitter 3, 4 0.17 UI
TJ9.953_QPLL Total jitter 2, 4 9.953 Gb/s 0.28 UI
DJ9.953_QPLL Deterministic jitter 2, 4 0.17 UI
TJ9.953_CPLL Total jitter 3, 4 9.953 Gb/s 0.33 UI
DJ9.953_CPLL Deterministic jitter 3, 4 0.17 UI
TJ8.0 Total jitter 3, 4 8.0 Gb/s 0.32 UI
DJ8.0 Deterministic jitter 3, 4 0.17 UI
TJ6.6 Total jitter 3, 4 6.6 Gb/s 0.30 UI
DJ6.6 Deterministic jitter 3, 4 0.15 UI
TJ5.0 Total jitter 3, 4 5.0 Gb/s 0.30 UI
DJ5.0 Deterministic jitter 3, 4 0.15 UI
TJ4.25 Total jitter 3, 4 4.25 Gb/s 0.30 UI
DJ4.25 Deterministic jitter 3, 4 0.15 UI
TJ3.20 Total jitter 3, 4 3.20 Gb/s 5 0.20 UI
DJ3.20 Deterministic jitter 3, 4 0.10 UI
TJ2.5 Total jitter 3, 4 2.5 Gb/s 6 0.20 UI
DJ2.5 Deterministic jitter 3, 4 0.10 UI
TJ1.25 Total jitter 3, 4 1.25 Gb/s 7 0.15 UI
DJ1.25 Deterministic jitter 3, 4 0.06 UI
TJ500 Total jitter 3, 4 500 Mb/s 8 0.10 UI
DJ500 Deterministic jitter 3, 4 0.03 UI
  1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTY Quad) at maximum line rate.
  2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
  3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
  4. All jitter values are based on a bit-error ratio of 10–12.
  5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
  6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
  7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
  8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.
Table 8. GTY Transceiver Receiver Switching Characteristics
Symbol Description Condition Min Typ Max Units
FGTYRX Serial data rate 0.500 FGTYMAX Gb/s
RXSST Receiver spread-spectrum tracking 1 Modulated at 33 kHz –5000 0 ppm
RXRL Run length (CID) 256 UI
RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 1250 ppm
Bit rates > 6.6 Gb/s and ≤ 8.0 Gb/s –700 700 ppm
Bit rates > 8.0 Gb/s –200 200 ppm
SJ Jitter Tolerance 2
JT_SJ16.375 Sinusoidal jitter (QPLL) 3 16.375 Gb/s 0.30 UI
JT_SJ15.0 Sinusoidal jitter (QPLL) 3 15.0 Gb/s 0.30 UI
JT_SJ14.1 Sinusoidal jitter (QPLL) 3 14.1 Gb/s 0.30 UI
JT_SJ13.1 Sinusoidal jitter (QPLL) 3 13.1 Gb/s 0.30 UI
JT_SJ12.5 Sinusoidal jitter (QPLL) 3 12.5 Gb/s 0.30 UI
JT_SJ11.3 Sinusoidal jitter (QPLL) 3 11.3 Gb/s 0.30 UI
JT_SJ10.32_QPLL Sinusoidal jitter (QPLL) 3 10.32 Gb/s 0.30 UI
JT_SJ10.32_CPLL Sinusoidal jitter (CPLL) 3 10.32 Gb/s 0.30 UI
JT_SJ9.953_QPLL Sinusoidal jitter (QPLL) 3 9.953 Gb/s 0.30 UI
JT_SJ9.953_CPLL Sinusoidal jitter (CPLL) 3 9.953 Gb/s 0.30 UI
JT_SJ8.0 Sinusoidal jitter (CPLL) 3 8.0 Gb/s 0.42 UI
JT_SJ6.6 Sinusoidal jitter (CPLL) 3 6.6 Gb/s 0.44 UI
JT_SJ5.0 Sinusoidal jitter (CPLL) 3 5.0 Gb/s 0.44 UI
JT_SJ4.25 Sinusoidal jitter (CPLL) 3 4.25 Gb/s 0.44 UI
JT_SJ3.2 Sinusoidal jitter (CPLL) 3 3.2 Gb/s 4 0.45 UI
JT_SJ2.5 Sinusoidal jitter (CPLL) 3 2.5 Gb/s 5 0.30 UI
JT_SJ1.25 Sinusoidal jitter (CPLL) 3 1.25 Gb/s 6 0.30 UI
JT_SJ500 Sinusoidal jitter (CPLL) 3 500 Mb/s 7 0.30 UI
SJ Jitter Tolerance with Stressed Eye 2
JT_TJSE3.2 Total jitter with stressed eye 8 3.2 Gb/s 0.70 UI
JT_TJSE6.6 6.6 Gb/s 0.70 UI
JT_SJSE3.2 Sinusoidal jitter with stressed eye 8 3.2 Gb/s 0.10 UI
JT_SJSE6.6 6.6 Gb/s 0.10 UI
  1. Using RXOUT_DIV = 1, 2, and 4.
  2. All jitter values are based on a bit error ratio of 10–12.
  3. The frequency of the injected sinusoidal jitter is 80 MHz.
  4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2.
  5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2.
  6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4.
  7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8.
  8. Composite jitter with RX equalizer enabled. DFE disabled.