I/O Levels

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. SelectIO DC Input and Output Levels For HD I/O Banks
I/O Standard 1, 2 VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.0 –8.0
HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.0 –8.0
HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 3 Note 3
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 4 Note 4
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 4 Note 4
LVCMOS25 –0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS33 –0.300 0.800 2.000 3.400 0.400 VCCO – 0.400 Note 4 Note 4
LVTTL –0.300 0.800 2.000 3.400 0.400 2.400 Note 4 Note 4
SSTL12 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 14.25 –14.25
SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.9 –8.9
SSTL135_II –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 13.0 –13.0
SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 8.9 –8.9
SSTL15_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 13.0 –13.0
SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 8.0 –8.0
SSTL18_II –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.600 VCCO/2 + 0.600 13.4 –13.4
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
  3. Supported drive strengths of 4, 8, or 12 mA in HD I/O banks.
  4. Supported drive strengths of 4, 8, 12, or 16 mA in HD I/O banks.
Table 2. SelectIO DC Input and Output Levels for HP I/O Banks
I/O Standard 1, 2, 3 VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 5.8 –5.8
HSTL_I_12 –0.300 VREF – 0.080 VREF + 0.080 VCCO + 0.300 25% VCCO 75% VCCO 4.1 –4.1
HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 6.2 –6.2
HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5
LVDCI_15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 7.0 –7.0
LVDCI_18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 7.0 –7.0
SSTL12 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.0 –8.0
SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 9.0 –9.0
SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 10.0 –10.0
SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 7.0 –7.0
MIPI_DPHY_ DCI_LP 6 –0.300 0.550 0.880 VCCO + 0.300 0.050 1.100 0.01 –0.01
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
  3. POD10 and POD12 DC input and output levels are shown in Table 3, Table 8, and Table 9.
  4. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.
  5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.
  6. Low-power option for MIPI_DPHY_DCI.
Table 3. DC Input Levels for Single-ended POD10 and POD12 I/O Standards
I/O Standard 1, 2 VIL VIH
V, Min V, Max V, Min V, Max
POD10 –0.300 VREF – 0.068 VREF + 0.068 VCCO + 0.300
POD12 –0.300 VREF – 0.068 VREF + 0.068 VCCO + 0.300
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
Table 4. Differential SelectIO DC Input and Output Levels
I/O Standard VICM (V) 1 VID (V) 2 VILHS 3 VIHHS 3 VOCM (V) 4 VOD (V) 5
Min Typ Max Min Typ Max Min Max Min Typ Max Min Typ Max
SUB_LVDS 8 0.500 0.900 1.300 0.070 0.700 0.900 1.100 0.100 0.150 0.200
LVPECL 0.300 1.200 1.425 0.100 0.350 0.600
SLVS_400_18 0.070 0.200 0.330 0.140 0.450
SLVS_400_25 0.070 0.200 0.330 0.140 0.450
MIPI_DPHY_ DCI_HS 9 0.070 0.330 0.070 –0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270
  1. VICM is the input common mode voltage.
  2. VID is the input differential voltage (Q – Q).
  3. VIHHS and VILHS are the single-ended input high and low voltages, respectively.
  4. VOCM is the output common mode voltage.
  5. VOD is the output differential voltage (Q – Q).
  6. LVDS_25 is specified in Table 1.
  7. LVDS is specified in Table 1.
  8. The SUB_LVDS receiver is supported in HP I/O and HD I/O banks. The SUB_LVDS transmitter is supported only in HP I/O banks.
  9. High-speed option for MIPI_DPHY_DCI. The VID maximum is aligned with the standard’s specification. A higher VID is acceptable as long as the VIN specification is also met.
Table 5. Complementary Differential SelectIO DC Input and Output Levels for HD I/O Banks
I/O Standard VICM (V) 1 VID (V) 2 VOL (V) 3 VOH (V) 4 IOL IOH
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I 0.300 0.750 1.125 0.100 0.400 VCCO – 0.400 8.0 –8.0
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 0.400 VCCO – 0.400 8.0 –8.0
DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.1 –0.1
DIFF_SSTL12 0.300 0.600 0.850 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 14.25 –14.25
DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 –8.9
DIFF_SSTL135_II 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0
DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 –8.9
DIFF_SSTL15_II 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 –13.0
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.0 –8.0
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 –13.4
  1. VICM is the input common mode voltage.
  2. VID is the input differential voltage.
  3. VOL is the single-ended low-output voltage.
  4. VOH is the single-ended high-output voltage.
Table 6. Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks
I/O Standard 1 VICM (V) 2 VID (V) 3 VOL (V) 4 VOH (V) 5 IOL IOH
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I 0.680 VCCO/2 (VCCO/2) + 0.150 0.100 0.400 VCCO – 0.400 5.8 –5.8
DIFF_HSTL_I_12 0.400 x VCCO VCCO/2 0.600 x VCCO 0.100 0.250 x VCCO 0.750 x VCCO 4.1 –4.1
DIFF_HSTL_I_18 (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 0.400 VCCO – 0.400 6.2 –6.2
DIFF_HSUL_12 (VCCO/2) – 0.120 VCCO/2 (VCCO/2) + 0.120 0.100 20% VCCO 80% VCCO 0.1 –0.1
DIFF_SSTL12 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.0 –8.0
DIFF_SSTL135 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 9.0 –9.0
DIFF_SSTL15 (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 10.0 –10.0
DIFF_SSTL18_I (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 (VCCO/2) – 0.470 (VCCO/2) + 0.470 7.0 –7.0
  1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 7, Table 8, and Table 9.
  2. VICM is the input common mode voltage.
  3. VID is the input differential voltage.
  4. VOL is the single-ended low-output voltage.
  5. VOH is the single-ended high-output voltage.
Table 7. DC Input Levels for Differential POD10 and POD12 I/O Standards
I/O Standard 1, 2 VICM (V) VID (V)
Min Typ Max Min Max
DIFF_POD10 0.63 0.70 0.77 0.14
DIFF_POD12 0.76 0.84 0.92 0.16
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
Table 8. DC Output Levels for Single-ended and Differential POD10 and POD12 Standards
Symbol Description 1, 2 VOUT Min Typ Max Units
ROL Pull-down resistance VOM_DC (as described in Table 9) 36 40 44 Ω
ROH Pull-up resistance VOM_DC (as described in Table 9) 36 40 44 Ω
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
Table 9. Definitions for DC Output Levels for Single-ended and Differential POD10 and POD12 Standards
Symbol Description All Speed Grades Units
VOM_DC DC output Mid measurement level (for IV curve linearity) 0.8 x VCCO V