IOB High Density (HD) Switching Characteristics

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. IOB High Density (HD) Switching Characteristics
I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD Units
0.85V 0.72V 0.85V 0.72V 0.85V 0.72V
-2 -1 -1 -2 -1 -1 -2 -1 -1
DIFF_HSTL_I_18_F 0.978 1.058 1.058 1.574 1.718 2.101 1.160 1.271 1.544 ns
DIFF_HSTL_I_18_S 0.978 1.058 1.058 1.805 1.950 2.333 1.748 1.867 2.104 ns
DIFF_HSTL_I_F 0.978 1.058 1.058 1.611 1.762 2.145 1.313 1.417 1.668 ns
DIFF_HSTL_I_S 0.978 1.058 1.058 1.798 1.913 2.296 1.630 1.780 1.986 ns
DIFF_HSUL_12_F 0.911 0.977 0.977 1.573 1.703 2.086 1.222 1.335 1.578 ns
DIFF_HSUL_12_S 0.911 0.977 0.977 1.711 1.864 2.247 1.536 1.665 1.891 ns
DIFF_SSTL12_F 0.906 0.977 0.977 1.643 1.792 2.175 1.285 1.423 1.640 ns
DIFF_SSTL12_S 0.906 0.977 0.977 1.784 1.948 2.331 1.567 1.706 1.922 ns
DIFF_SSTL135_F 0.927 0.995 0.995 1.625 1.765 2.148 1.341 1.458 1.696 ns
DIFF_SSTL135_II_F 0.927 0.995 0.995 1.623 1.770 2.153 1.325 1.470 1.689 ns
DIFF_SSTL135_II_S 0.927 0.995 0.995 1.768 1.916 2.299 1.722 1.911 2.078 ns
DIFF_SSTL135_S 0.927 0.995 0.995 1.869 2.025 2.408 1.814 1.976 2.169 ns
DIFF_SSTL15_F 0.928 1.020 1.020 1.628 1.771 2.154 1.374 1.483 1.729 ns
DIFF_SSTL15_II_F 0.928 1.020 1.020 1.622 1.778 2.161 1.356 1.442 1.712 ns
DIFF_SSTL15_II_S 0.928 1.020 1.020 1.821 1.987 2.370 1.895 2.047 2.250 ns
DIFF_SSTL15_S 0.928 1.020 1.020 1.824 1.977 2.360 1.743 1.907 2.098 ns
DIFF_SSTL18_II_F 0.961 1.038 1.038 1.729 1.880 2.263 1.377 1.492 1.732 ns
DIFF_SSTL18_II_S 0.961 1.038 1.038 1.796 1.965 2.348 1.616 1.800 1.972 ns
DIFF_SSTL18_I_F 0.961 1.038 1.038 1.609 1.755 2.138 1.220 1.313 1.575 ns
DIFF_SSTL18_I_S 0.961 1.038 1.038 1.786 1.942 2.325 1.677 1.836 2.033 ns
HSTL_I_18_F 0.947 1.021 1.021 1.574 1.718 2.101 1.160 1.271 1.544 ns
HSTL_I_18_S 0.947 1.021 1.021 1.805 1.950 2.333 1.748 1.867 2.104 ns
HSTL_I_F 0.856 0.900 0.900 1.611 1.762 2.145 1.313 1.417 1.668 ns
HSTL_I_S 0.856 0.900 0.900 1.798 1.913 2.296 1.630 1.780 1.986 ns
HSUL_12_F 0.780 0.867 0.867 1.573 1.703 2.086 1.222 1.335 1.578 ns
HSUL_12_S 0.780 0.867 0.867 1.711 1.864 2.247 1.536 1.665 1.891 ns
LVCMOS12_F_12 0.918 0.976 0.976 1.689 1.856 2.239 1.202 1.317 1.557 ns
LVCMOS12_F_4 0.918 0.976 0.976 1.742 1.922 2.305 1.353 1.478 1.708 ns
LVCMOS12_F_8 0.918 0.976 0.976 1.714 1.879 2.262 1.292 1.432 1.647 ns
LVCMOS12_S_12 0.918 0.976 0.976 2.073 2.247 2.630 1.581 1.717 1.937 ns
LVCMOS12_S_4 0.918 0.976 0.976 1.979 2.182 2.565 1.633 1.772 1.989 ns
LVCMOS12_S_8 0.918 0.976 0.976 2.205 2.406 2.789 1.767 1.928 2.123 ns
LVCMOS15_F_12 0.905 0.958 0.958 1.713 1.892 2.275 1.275 1.428 1.630 ns
LVCMOS15_F_16 0.905 0.958 0.958 1.722 1.881 2.264 1.260 1.407 1.615 ns
LVCMOS15_F_4 0.905 0.958 0.958 1.825 1.959 2.342 1.453 1.557 1.809 ns
LVCMOS15_F_8 0.905 0.958 0.958 1.778 1.930 2.313 1.378 1.458 1.733 ns
LVCMOS15_S_12 0.905 0.958 0.958 1.991 2.139 2.522 1.516 1.648 1.871 ns
LVCMOS15_S_16 0.905 0.958 0.958 2.172 2.389 2.772 1.707 1.888 2.062 ns
LVCMOS15_S_4 0.905 0.958 0.958 2.313 2.483 2.866 1.952 2.123 2.307 ns
LVCMOS15_S_8 0.905 0.958 0.958 2.170 2.400 2.783 1.817 1.984 2.173 ns
LVCMOS18_F_12 0.915 0.958 0.958 1.805 1.962 2.345 1.383 1.471 1.738 ns
LVCMOS18_F_16 0.915 0.958 0.958 1.785 1.917 2.300 1.338 1.446 1.693 ns
LVCMOS18_F_4 0.915 0.958 0.958 1.868 2.013 2.396 1.472 1.599 1.832 ns
LVCMOS18_F_8 0.915 0.958 0.958 1.797 1.979 2.362 1.384 1.487 1.739 ns
LVCMOS18_S_12 0.915 0.958 0.958 2.201 2.408 2.791 1.762 1.894 2.118 ns
LVCMOS18_S_16 0.915 0.958 0.958 2.173 2.362 2.745 1.702 1.834 2.057 ns
LVCMOS18_S_4 0.915 0.958 0.958 2.346 2.567 2.950 1.951 2.092 2.306 ns
LVCMOS18_S_8 0.915 0.958 0.958 2.292 2.511 2.894 1.848 2.008 2.204 ns
LVCMOS25_F_12 0.988 1.042 1.042 2.153 2.453 2.836 1.692 1.856 2.047 ns
LVCMOS25_F_16 0.988 1.042 1.042 2.105 2.406 2.789 1.623 1.786 1.979 ns
LVCMOS25_F_4 0.988 1.042 1.042 2.344 2.554 2.937 1.842 2.039 2.197 ns
LVCMOS25_F_8 0.988 1.042 1.042 2.184 2.516 2.899 1.726 1.910 2.081 ns
LVCMOS25_S_12 0.988 1.042 1.042 2.558 2.840 3.223 1.971 2.194 2.327 ns
LVCMOS25_S_16 0.988 1.042 1.042 2.449 2.740 3.123 1.852 2.063 2.207 ns
LVCMOS25_S_4 0.988 1.042 1.042 2.770 3.066 3.449 2.224 2.458 2.579 ns
LVCMOS25_S_8 0.988 1.042 1.042 2.663 2.963 3.346 2.091 2.373 2.446 ns
LVCMOS33_F_12 1.154 1.213 1.213 2.415 2.651 3.034 1.754 1.915 2.109 ns
LVCMOS33_F_16 1.154 1.213 1.213 2.383 2.603 2.986 1.734 1.869 2.089 ns
LVCMOS33_F_4 1.154 1.213 1.213 2.541 2.765 3.148 1.932 2.135 2.287 ns
LVCMOS33_F_8 1.154 1.213 1.213 2.603 2.822 3.205 1.937 2.130 2.294 ns
LVCMOS33_S_12 1.154 1.213 1.213 2.705 3.047 3.430 2.049 2.318 2.404 ns
LVCMOS33_S_16 1.154 1.213 1.213 2.714 3.024 3.407 2.028 2.232 2.383 ns
LVCMOS33_S_4 1.154 1.213 1.213 2.999 3.340 3.723 2.320 2.610 2.675 ns
LVCMOS33_S_8 1.154 1.213 1.213 2.929 3.260 3.643 2.260 2.532 2.616 ns
LVDS_25 1.003 1.116 1.116 N/A N/A N/A N/A N/A N/A ns
LVPECL 1.003 1.116 1.116 N/A N/A N/A N/A N/A N/A ns
LVTTL_F_12 1.164 1.223 1.223 2.415 2.651 3.034 1.754 1.915 2.109 ns
LVTTL_F_16 1.164 1.223 1.223 2.464 2.732 3.115 1.750 1.986 2.117 ns
LVTTL_F_4 1.164 1.223 1.223 2.541 2.765 3.148 1.932 2.135 2.287 ns
LVTTL_F_8 1.164 1.223 1.223 2.582 2.787 3.170 1.910 2.063 2.265 ns
LVTTL_S_12 1.164 1.223 1.223 2.731 3.075 3.458 2.072 2.343 2.427 ns
LVTTL_S_16 1.164 1.223 1.223 2.714 3.024 3.407 2.028 2.232 2.383 ns
LVTTL_S_4 1.164 1.223 1.223 2.999 3.340 3.723 2.320 2.610 2.675 ns
LVTTL_S_8 1.164 1.223 1.223 2.929 3.260 3.643 2.260 2.532 2.616 ns
SLVS_400_25 1.020 1.136 1.136 N/A N/A N/A N/A N/A N/A ns
SSTL12_F 0.780 0.867 0.867 1.643 1.792 2.175 1.285 1.423 1.640 ns
SSTL12_S 0.780 0.867 0.867 1.784 1.948 2.331 1.567 1.706 1.922 ns
SSTL135_F 0.798 0.881 0.881 1.625 1.765 2.148 1.341 1.458 1.696 ns
SSTL135_II_F 0.798 0.881 0.881 1.623 1.770 2.153 1.325 1.470 1.689 ns
SSTL135_II_S 0.798 0.881 0.881 1.768 1.916 2.299 1.722 1.911 2.078 ns
SSTL135_S 0.798 0.881 0.881 1.869 2.025 2.408 1.814 1.976 2.169 ns
SSTL15_F 0.838 0.880 0.880 1.612 1.754 2.137 1.357 1.464 1.713 ns
SSTL15_II_F 0.838 0.880 0.880 1.622 1.778 2.161 1.356 1.442 1.712 ns
SSTL15_II_S 0.838 0.880 0.880 1.821 1.987 2.370 1.895 2.047 2.250 ns
SSTL15_S 0.838 0.880 0.880 1.824 1.977 2.360 1.743 1.907 2.098 ns
SSTL18_II_F 0.947 1.021 1.021 1.729 1.880 2.263 1.377 1.492 1.732 ns
SSTL18_II_S 0.947 1.021 1.021 1.796 1.965 2.348 1.616 1.800 1.972 ns
SSTL18_I_F 0.947 1.021 1.021 1.609 1.755 2.138 1.220 1.313 1.575 ns
SSTL18_I_S 0.947 1.021 1.021 1.786 1.942 2.325 1.677 1.836 2.033 ns
SUB_LVDS 1.002 1.036 1.036 N/A N/A N/A N/A N/A N/A ns