Input Delay Measurement Methodology

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English

The following table shows the test setup parameters used for measuring input delay.

Table 1. Input Delay Measurement Methodology
Description I/O Standard Attribute VL 1, 2 VH 1, 2 VMEAS 1, 4 VREF 1, 3, 5
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6
LVCMOS, LVDCI, HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 0.1 1.4 0.75
LVCMOS, LVDCI, HSLVDCI, 1.8V LVCMOS18, LVDCI_18, HSLVDCI_18 0.1 1.7 0.9
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65
LVTTL, 3.3V LVTTL 0.1 3.2 1.65
HSTL (high-speed transceiver logic), class I, 1.2V HSTL_I_12 VREF – 0.25 VREF + 0.25 VREF 0.6
HSTL, class I, 1.5V HSTL_I VREF – 0.325 VREF + 0.325 VREF 0.75
HSTL, class I, 1.8V HSTL_I_18 VREF – 0.4 VREF + 0.4 VREF 0.9
HSUL (high-speed unterminated logic), 1.2V HSUL_12 VREF – 0.25 VREF + 0.25 VREF 0.6
SSTL12 (stub series terminated logic), 1.2V SSTL12 VREF – 0.25 VREF + 0.25 VREF 0.6
SSTL135 and SSTL135 class II, 1.35V SSTL135, SSTL135_II VREF – 0.2875 VREF + 0.2875 VREF 0.675
SSTL15 and SSTL15 class II, 1.5V SSTL15, SSTL15_II VREF – 0.325 VREF + 0.325 VREF 0.75
SSTL18, class I and II, 1.8V SSTL18_I, SSTL18_II VREF – 0.4 VREF + 0.4 VREF 0.9
POD10, 1.0V POD10 VREF – 0.2 VREF + 0.2 VREF 0.7
POD12, 1.2V POD12 VREF – 0.24 VREF + 0.24 VREF 0.84
DIFF_HSTL, class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.25 0.6 + 0.25 0 6
DIFF_HSTL, class I, 1.5V DIFF_HSTL_I 0.75 – 0.325 0.75 + 0.325 0 6
DIFF_HSTL, class I, 1.8V DIFF_HSTL_I_18 0.9 – 0.4 0.9 + 0.4 0 6
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.25 0.6 + 0.25 0 6
DIFF_SSTL, 1.2V DIFF_SSTL12 0.6 – 0.25 0.6 + 0.25 0 6
DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V DIFF_SSTL135, DIFF_SSTL135_II 0.675 – 0.2875 0.675 + 0.2875 0 6
DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V DIFF_SSTL15, DIFF_SSTL15_II 0.75 – 0.325 0.75 + 0.325 0 6
DIFF_SSTL18_I, DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 0.9 – 0.4 0.9 + 0.4 0 6
DIFF_POD10, 1.0V DIFF_POD10 0.5 – 0.2 0.5 + 0.2 0 6
DIFF_POD12, 1.2V DIFF_POD12 0.6 – 0.25 0.6 + 0.25 0 6
LVDS (low-voltage differential signaling), 1.8V LVDS 0.9 – 0.125 0.9 + 0.125 0 6
LVDS_25, 2.5V LVDS_25 1.25 – 0.125 1.25 + 0.125 0 6
SUB_LVDS, 1.8V SUB_LVDS 0.9 – 0.125 0.9 + 0.125 0 6
SLVS, 1.8V SLVS_400_18 0.9 – 0.125 0.9 + 0.125 0 6
SLVS, 2.5V SLVS_400_25 1.25 – 0.125 1.25 + 0.125 0 6
LVPECL, 2.5V LVPECL 1.25 – 0.125 1.25 + 0.125 0 6
MIPI D-PHY (high speed) 1.2V MIPI_DPHY_DCI_HS 0.2 – 0.125 0.2 + 0.125 0 6
MIPI D-PHY (low power) 1.2V MIPI_DPHY_DCI_LP 0.715 – 0.2 0.715 + 0.2 0 6
  1. The input delay measurement methodology parameters for LVDCI/HSLVDCI are the same for LVCMOS standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards.
  2. Input waveform switches between VL and VH.
  3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical.
  4. Input voltage level from which measurement starts.
  5. This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models and/or noted in Figure 1.
  6. The value given is the differential input voltage.