Input/Output Delay Switching Characteristics

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. Input/Output Delay Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1

FREFCLK

Reference clock frequency for IDELAYCTRL (component mode) 300 to 800 MHz
Reference clock frequency when using BITSLICE_CONTROL with REFCLK (in native mode (for RX_BITSLICE only)) 300 to 800 MHz
Reference clock frequency for BITSLICE_CONTROL with PLL_CLK (in native mode) 1 300 to 2666.67 300 to 2400 300 to 2133 MHz

TMINPER_CLK

Minimum period for IODELAY clock 3.195 3.195 3.195 ns
TMINPER_RST Minimum reset pulse width 52.00 ns
TIDELAY_RESOLUTION/ TODELAY_RESOLUTION IDELAY/ODELAY chain resolution 2.1 to 12 ps
  1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the minimum frequency is PLL_FVCOMIN/2.