Integrated Interface Block for PCI Express Designs

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English

More information and documentation on solutions for PCI Express® designs can be found at PCI Express . The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Artix UltraScale+ FPGA.

Table 1. Maximum Performance for PCIE4-based PCI Express Designs
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 MHz
FCORECLK Core clock maximum frequency 500.00 500.00 250.00 MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 MHz
FMCAPCLK MCAP clock maximum frequency 1 125.00 125.00 125.00 MHz
  1. For information on tandem PCIe support, see the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).
The PCIE4C blocks in the XCAU10P and XCAU15P include support for the CCIX protocol.
Table 2. Maximum Performance for PCIE4C-based PCI Express and CCIX Designs
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 MHz
FCORECLK Core clock maximum frequency 500.00 500.00 250.00 MHz
FCORECLKCCIX CCIX TL interface clock maximum frequency 500.00 500.00 N/A MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 MHz
FMCAPCLK MCAP clock maximum frequency 1 125.00 125.00 125.00 MHz
  1. For information on tandem PCIe support in XCAU10P and XCAU15P devices, see the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).