LVDS DC Specifications (LVDS_25)

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-09-06
Revision
1.3 English

The LVDS_25 standard is available in the HD I/O banks. See the UltraScale Architecture SelectIO Resources User Guide (UG571) for more information.

Table 1. LVDS_25 DC Specifications
Symbol DC Parameter Min Typ Max Units
VCCO 1 Supply voltage 2.375 2.500 2.625 V
VIDIFF Differential input voltage:

(Q – Q), Q = High

(Q – Q), Q = High

100 350 600 2 mV
VICM Input common-mode voltage 0.300 1.200 1.425 V
  1. LVDS_25 in HD I/O banks supports inputs only. LVDS_25 inputs without internal termination have no VCCO requirements. Any VCCO can be chosen as long as the input voltage levels do not violate the Recommended Operating Condition (Table 1) specification for the VIN I/O pin voltage.
  2. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.